公开(公告)号：US07236012B2

公开(公告)日：2007-06-26

申请号：US10970016

申请日：2004-10-22

Applicant: Geun-hee Cho ,  Jung-bae Lee

Inventor： Geun-hee Cho ,  Jung-bae Lee

IPC: H03K19/0175

CPC classification number: G11C7/1051 ,  G11C7/1057

Abstract: A data output driver of a semiconductor memory device can minimize a difference in slew rate of an output signal according to a selected bit organization. The data output driver includes a pull-up driver and a pull-down driver. The pull-up driver pulls up an output terminal and the pull-down driver pulls down the output terminal. In particular, current driving capabilities of the pull-up driver and/or the pull-down driver are changed in response to bit organization information signals of the semiconductor memory device.

Abstract translation: 半导体存储器件的数据输出驱动器可以根据所选位组织来最小化输出信号的转换速率差。 数据输出驱动器包括一个上拉驱动器和一个下拉驱动器。 上拉驱动器拉出输出端子，下拉驱动器拉出输出端子。 特别地，上拉驱动器和/或下拉驱动器的当前驱动能力响应于半导体存储器件的位组织信息信号而改变。

公开(公告)号：US20050105294A1

公开(公告)日：2005-05-19

申请号：US10970016

申请日：2004-10-22

Applicant: Geun-hee Cho ,  Jung-bae Lee

Inventor： Geun-hee Cho ,  Jung-bae Lee

IPC: G11C11/40 ,  F21V1/00 ,  G11C7/10

CPC classification number: G11C7/1051 ,  G11C7/1057

Abstract: A data output driver of a semiconductor memory device can minimize a difference in slew rate of an output signal according to a selected bit organization. The data output driver includes a pull-up driver and a pull-down driver. The pull-up driver pulls up an output terminal and the pull-down driver pulls down the output terminal. In particular, current driving capabilities of the pull-up driver and/or the pull-down driver are changed in response to bit organization information signals of the semiconductor memory device.

Abstract translation: 半导体存储器件的数据输出驱动器可以根据所选位组织来最小化输出信号的转换速率差。 数据输出驱动器包括一个上拉驱动器和一个下拉驱动器。 上拉驱动器拉出输出端子，下拉驱动器拉出输出端子。 特别地，上拉驱动器和/或下拉驱动器的当前驱动能力响应于半导体存储器件的位组织信息信号而改变。

公开(公告)号：US06236619B1

公开(公告)日：2001-05-22

申请号：US09559265

申请日：2000-04-27

Applicant: Geun-hee Cho ,  Chi-wook Kim

Inventor： Geun-hee Cho ,  Chi-wook Kim

IPC: G11C800

CPC classification number: G11C7/1072 ,  G11C7/22

Abstract: A synchronous dynamic random access memory (SDRAM) semiconductor device is provided. The SDRAM has a write-interrupt-write function and includes a first memory block for storing data, a first sense amplifier for sensing the data stored in the first memory block, first and second groups of input/output lines, connected to the first sense amplifier, and a write-interrupt-write signal generating portion for receiving an externally input write signal and an internal clock signal to generate a write-interrupt-write signal, and for providing the write-interrupt-write signal to the first sense amplifier. When an externally input data is written to the first memory block through the first group of input/output lines in response to the write signal enabled at a first point in time and the write signal is enabled at a second point in time to write data to the first memory block through the second group of input/output lines, the write-interrupt write signal generator enables the write-interrupt-write signal after a predetermined number of cycles of the internal clock signal from the second point in time at which the write signal is enabled, thereby immediately precharging the first group of input/output lines. As a result of this design, the write-interrupt-write function can be accurately carried out.

Abstract translation: 提供了一种同步动态随机存取存储器（SDRAM）半导体器件。 SDRAM具有写入中断写入功能，并且包括用于存储数据的第一存储器块，用于感测存储在第一存储器块中的数据的第一读出放大器，连接到第一感测的第一和第二组输入/输出线 放大器以及用于接收外部输入写入信号和内部时钟信号的写入中断写入信号产生部分，以产生写入中断写入信号，并向第一读出放大器提供写入中断写入信号。 当通过第一组输入/输出线将外部输入数据写入到第一存储块时，响应于在第一时间点使能写入信号，并且写入信号在第二时间点被使能以将数据写入 通过第二组输入/输出线的第一存储块，写中断写信号发生器在来自第二时间点的预定数量的内部时钟信号的周期之后启用写中断写信号， 信号被使能，从而立即对第一组输入/输出线进行预充电。 作为这种设计的结果，可以准确地执行写入中断写入功能。