公开(公告)号：US07236012B2

公开(公告)日：2007-06-26

申请号：US10970016

申请日：2004-10-22

Applicant: Geun-hee Cho ,  Jung-bae Lee

Inventor： Geun-hee Cho ,  Jung-bae Lee

IPC: H03K19/0175

CPC classification number: G11C7/1051 ,  G11C7/1057

Abstract: A data output driver of a semiconductor memory device can minimize a difference in slew rate of an output signal according to a selected bit organization. The data output driver includes a pull-up driver and a pull-down driver. The pull-up driver pulls up an output terminal and the pull-down driver pulls down the output terminal. In particular, current driving capabilities of the pull-up driver and/or the pull-down driver are changed in response to bit organization information signals of the semiconductor memory device.

Abstract translation: 半导体存储器件的数据输出驱动器可以根据所选位组织来最小化输出信号的转换速率差。 数据输出驱动器包括一个上拉驱动器和一个下拉驱动器。 上拉驱动器拉出输出端子，下拉驱动器拉出输出端子。 特别地，上拉驱动器和/或下拉驱动器的当前驱动能力响应于半导体存储器件的位组织信息信号而改变。

公开(公告)号：US20050105294A1

公开(公告)日：2005-05-19

申请号：US10970016

申请日：2004-10-22

Applicant: Geun-hee Cho ,  Jung-bae Lee

Inventor： Geun-hee Cho ,  Jung-bae Lee

IPC: G11C11/40 ,  F21V1/00 ,  G11C7/10

CPC classification number: G11C7/1051 ,  G11C7/1057

Abstract: A data output driver of a semiconductor memory device can minimize a difference in slew rate of an output signal according to a selected bit organization. The data output driver includes a pull-up driver and a pull-down driver. The pull-up driver pulls up an output terminal and the pull-down driver pulls down the output terminal. In particular, current driving capabilities of the pull-up driver and/or the pull-down driver are changed in response to bit organization information signals of the semiconductor memory device.

Abstract translation: 半导体存储器件的数据输出驱动器可以根据所选位组织来最小化输出信号的转换速率差。 数据输出驱动器包括一个上拉驱动器和一个下拉驱动器。 上拉驱动器拉出输出端子，下拉驱动器拉出输出端子。 特别地，上拉驱动器和/或下拉驱动器的当前驱动能力响应于半导体存储器件的位组织信息信号而改变。

公开(公告)号：US08446988B2

公开(公告)日：2013-05-21

申请号：US13280456

申请日：2011-10-25

Applicant: Hoe-ju Chung ,  Jung-bae Lee

Inventor： Hoe-ju Chung ,  Jung-bae Lee

IPC: H04L27/06

CPC classification number: H04L25/0264 ,  H04L25/0272

Abstract: In a communication system, data is selectively transmitted using single-ended or differential signaling. The data is transmitted in relation to a plurality of clock signals having different relative phases. When the data is transmitted using single-ended signaling, data on adjacent signal lines undergo logic transitions at different times in relation to the plurality of clock signals.

Abstract translation: 在通信系统中，使用单端或差分信令有选择地发送数据。 相对于具有不同相对相位的多个时钟信号发送数据。 当使用单端信令发送数据时，相邻信号线上的数据相对于多个时钟信号在不同时刻进行逻辑转换。

公开(公告)号：US20130016574A1

公开(公告)日：2013-01-17

申请号：US13548484

申请日：2012-07-13

Applicant: Jung-sik Kim ,  Cheol Kim ,  Sang-ho Shin ,  Jung-bae Lee ,  Chan-yong Lee ,  Sung-min Yim ,  Tae-seong Jang ,  Joo-sun Choi

Inventor： Jung-sik Kim ,  Cheol Kim ,  Sang-ho Shin ,  Jung-bae Lee ,  Chan-yong Lee ,  Sung-min Yim ,  Tae-seong Jang ,  Joo-sun Choi

IPC: G11C29/08 ,  G11C7/00

CPC classification number: G11C29/50016 ,  G11C5/04 ,  G11C11/40 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40622 ,  G11C2211/4061 ,  G11C2211/4065

Abstract: A semiconductor memory device having improved refresh characteristics includes a memory array including a plurality of memory cells; a test unit configured to test refresh characteristics of the memory array and generate a first fail address signal; a storage unit configured to store the first fail address signal; and a refresh unit configured to perform a refresh operation on the memory array, wherein the refresh unit is configured to receive the first fail address signal from the storage unit, perform the refresh operation on a first memory cell that does not correspond to the first fail address signal according to a first period, and perform the refresh operation on a second memory cell that corresponds to the first fail address signal according to a second period that is shorter than the first period.

Abstract translation: 具有改进的刷新特性的半导体存储器件包括包括多个存储器单元的存储器阵列; 测试单元，被配置为测试所述存储器阵列的刷新特性并产生第一故障地址信号; 存储单元，被配置为存储所述第一失败地址信号; 以及刷新单元，被配置为对所述存储器阵列执行刷新操作，其中所述刷新单元被配置为从所述存储单元接收所述第一故障地址信号，对与所述第一故障不对应的第一存储器单元执行刷新操作 根据第一期间的地址信号，根据比第一期间短的第二期间对与第一失败地址信号对应的第二存储单元进行刷新动作。

公开(公告)号：US07957217B2

公开(公告)日：2011-06-07

申请号：US12266716

申请日：2008-11-07

Applicant: Moon-sook Park ,  Hoe-ju Chung ,  Jung-bae Lee

Inventor： Moon-sook Park ,  Hoe-ju Chung ,  Jung-bae Lee

IPC: G11C8/00

CPC classification number: G11C5/147 ,  G11C5/04

Abstract: The invention relates generally to a multi-chip package (MCP) memory device, and more particularly, but without limitation, to a MCP memory device having a reduced size. In one embodiment, the MCP memory device includes: a transfer memory chip; and a plurality of memory chips coupled to the transfer memory chip, each of the plurality of memory chips including an internal voltage generating circuit, the transfer memory chip configured to receive a plurality of command signals from outside the MCP memory device, the transfer memory chip further configured to output a plurality of control signals to the plurality of memory chips based on the plurality of command signals. Embodiments of the invention also relate to a method of controlling an internal voltage of the MCP memory device.

Abstract translation: 本发明一般涉及一种多芯片封装（MCP）存储器件，尤其涉及但不限于具有减小尺寸的MCP存储器件。 在一个实施例中，MCP存储器件包括：传送存储器芯片; 以及多个存储器芯片，其耦合到所述传送存储器芯片，所述多个存储器芯片中的每一个包括内部电压产生电路，所述传送存储器芯片被配置为从所述MCP存储器设备的外部接收多个命令信号，所述传送存储器芯片 还被配置为基于所述多个命令信号将多个控制信号输出到所述多个存储器芯片。 本发明的实施例还涉及一种控制MCP存储器件的内部电压的方法。

公开(公告)号：US07948272B2

公开(公告)日：2011-05-24

申请号：US10990412

申请日：2004-11-18

Applicant: Dong-jin Lee ,  Jung-bae Lee ,  Kyu-hyoun Kim

Inventor： Dong-jin Lee ,  Jung-bae Lee ,  Kyu-hyoun Kim

IPC: H03K5/22

CPC classification number: H03K19/003

Abstract: An input buffer which detects an input signal. The input buffer including an output node, a first buffer, and a second buffer. The first buffer may control the voltage level of the output node when the voltage level of a reference voltage signal is equal to a predetermined voltage level. The second buffer may control the voltage level of the output node in response to the input signal when the voltage level of the reference voltage signal is lower than the predetermined voltage level. The second buffer may maintain the output node at a first level. The second buffer may include an output control section and a level control unit. The output control section may receive the input signal and generate a level output signal at a second level. The level control section may generate a control signal which maintains the output node at the first level, in response to the level output signal when the voltage level of the reference voltage signal is lower than the predetermined voltage level of the first voltage and may intercept the control signal when the voltage level of the reference voltage signal is equal to the predetermined voltage level.

Abstract translation: 输入缓冲器，用于检测输入信号。 输入缓冲器包括输出节点，第一缓冲器和第二缓冲器。 当参考电压信号的电压电平等于预定电压电平时，第一缓冲器可以控制输出节点的电压电平。 当参考电压信号的电压电平低于预定电压电平时，第二缓冲器可以响应于输入信号来控制输出节点的电压电平。 第二缓冲器可以将输出节点维持在第一级。 第二缓冲器可以包括输出控制部分和电平控制单元。 输出控制部分可以接收输入信号并产生第二电平的电平输出信号。 当参考电压信号的电压电平低于第一电压的预定电压电平时，电平控制部分可以响应于电平输出信号而产生将输出节点维持在第一电平的控制信号，并且可以拦截 当参考电压信号的电压电平等于预定电压电平时，控制信号。

公开(公告)号：US20080205113A1

公开(公告)日：2008-08-28

申请号：US12071745

申请日：2008-02-26

Applicant: UK-song Kang ,  Jung-bae Lee

Inventor： UK-song Kang ,  Jung-bae Lee

IPC: G11C5/06

CPC classification number: G11C5/025 ,  G11C5/04

Abstract: A multi memory chip stacked on a multi core CPU includes a plurality of memories, each memory corresponding to a CPU core from among the CPU cores and being configured to directly transmit data between the other memories of the multi memory chip.

Abstract translation: 堆叠在多核CPU上的多存储器芯片包括多个存储器，每个存储器对应于CPU核心中的CPU核心，并且被配置为直接在多存储器芯片的其他存储器之间传输数据。

公开(公告)号：US20050240718A1

公开(公告)日：2005-10-27

申请号：US11071586

申请日：2005-03-04

Applicant: Hoe-ju Chung ,  Jung-bae Lee

Inventor： Hoe-ju Chung ,  Jung-bae Lee

IPC: G11C7/10 ,  G06F12/00 ,  G06F12/14 ,  G06F12/16 ,  G06F13/00 ,  G06F13/42

CPC classification number: G06F13/4243

Abstract: Provided is a memory system and a method that can initialize a data channel at a high speed without the need to increase the number of pins in a semiconductor memory device, and not requiring a circuit to perform an initialization. The memory system includes a memory module equipped with a plurality of semiconductor memory devices; a memory controller controlling the semiconductor memory devices; and a data channel and a command/address channel connected between the plurality of semiconductor memory devices and the memory controller, wherein read latencies and write latencies of the plurality of semiconductor memory devices are controlled by the memory controller.

Abstract translation: 提供了一种可以高速初始化数据信道的存储器系统和方法，而不需要增加半导体存储器件中的引脚数量，并且不需要电路来执行初始化。 存储器系统包括配备有多个半导体存储器件的存储器模块; 控制半导体存储器件的存储器控​​制器; 以及连接在所述多个半导体存储器件和所述存储器控制器之间的数据通道和命令/地址通道，其中所述多个半导体存储器件的读取延迟和写入延迟由所述存储器控制器控制。

公开(公告)号：US06804163B2

公开(公告)日：2004-10-12

申请号：US10305986

申请日：2002-11-29

Applicant: Yun-sang Lee ,  Jung-bae Lee

Inventor： Yun-sang Lee ,  Jung-bae Lee

IPC: G11C800

CPC classification number: G11C7/12 ,  G11C5/025 ,  G11C7/06 ,  G11C7/10

Abstract: A semiconductor memory device that minimizes chip area is provided. The semiconductor memory device includes local input/output (I/O) lines, global I/O lines, and a memory core that is coupled between a bit line and a complementary bit line. The memory core includes a memory cell array, a bit line equalizer circuit, a PMOS sense amplifier (S/A), a PMOS S/A driving circuit for driving the PMOS S/A, a transmission gate circuit, an NMOS S/A, and an NMOS S/A driving circuit for driving the NMOS S/A. First and second transistors for connecting the local I/O lines to the global I/O lines are installed between adjacent bit lines. The PMOS S/A driving circuit, which is a first driving transistor, and the NMOS S/A driving circuit, which is a second driving transistor, are also installed between adjacent bit lines. Because the semiconductor memory device arranges a PMOS S/A driving circuit, an NMOS S/A driving circuit, and a gating circuit for connecting local I/O lines to global I/O lines, between adjacent bit lines, the chip area is reduced.

Abstract translation: 提供了最小化芯片面积的半导体存储器件。 半导体存储器件包括本地输入/输出（I / O）线，全局I / O线和耦合在位线和互补位线之间的存储器核。 存储器芯包括存储单元阵列，位线均衡器电路，PMOS读出放大器（S / A），用于驱动PMOS S / A的PMOS S / A驱动电路，传输门电路，NMOS S / A 以及用于驱动NMOS S / A的NMOS S / A驱动电路。 用于将本地I / O线连接到全局I / O线的第一和第二晶体管安装在相邻位线之间。 作为第一驱动晶体管的PMOS S / A驱动电路和作为第二驱动晶体管的NMOS S / A驱动电路也安装在相邻位线之间。 由于半导体存储器件在相邻位线之间配置PMOS S / A驱动电路，NMOS S / A驱动电路和用于将本地I / O线连接到全局I / O线的选通电路，芯片面积减小 。

公开(公告)号：US06414517B1

公开(公告)日：2002-07-02

申请号：US09685266

申请日：2000-10-10

Applicant: Kyu-hyoun Kim ,  Jung-bae Lee

Inventor： Kyu-hyoun Kim ,  Jung-bae Lee

IPC: H03K19094

CPC classification number: H04L25/028 ,  H04L25/0272

Abstract: An input buffer includes an amplifier circuit, such as a differential amplifier circuit, inverting amplifier circuit or pull-up/pull-down amplifier circuit. A momentary boost circuit is coupled to an input buffer input terminal, an input terminal of the amplifier circuit, and an output terminal of the amplifier circuit, and is operative to generate a boosted input signal at the input terminal of the amplifier circuit from an input signal at an input buffer input terminal for an interval that is terminated responsive to an output signal at the output terminal of the amplifier circuit. The momentary boost circuit may include a detector circuit coupled to the output terminal of the amplifier circuit and operative to generate a control signal responsive to a transition of the output signal, and a boost circuit, coupled between the input buffer input terminal and the input terminal of the amplifier circuit and operatively associated with the detector circuit, that receives the input signal at the input buffer input terminal and generates the boosted input signal at the input terminal of the amplifier circuit from the received input signal responsive to the control signal. For example, the boost circuit may include a capacitor coupled between the input buffer input terminal and the input terminal of the amplifier circuit, and a switch that couples and decouples the input terminal of the amplifier circuit to a reference voltage source responsive to the control signal. The detector circuit may be operative to generate a pulse responsive to a transition of the output signal, and the switch may be operative to couple the input terminal of the amplifier circuit to the reference voltage source responsive to the pulse.

Abstract translation: 输入缓冲器包括诸如差分放大器电路，反相放大器电路或上拉/下拉放大器电路的放大器电路。 瞬时升压电路耦合到输入缓冲器输入端子，放大器电路的输入端子和放大器电路的输出端子，并且可操作以从放大器电路的输入端在输入端产生升压输入信号 在输入缓冲器输入端子处，响应于在放大器电路的输出端子处的输出信号而终止的间隔的信号。 瞬时升压电路可以包括耦合到放大器电路的输出端的检测器电路，并且可操作以响应于输出信号的转变而产生控制信号，以及耦合在输入缓冲器输入端和输入端之间的升压电路 并且与检测器电路可操作地相关联，其在输入缓冲器输入端子处接收输入信号，并且响应于控制信号从所接收的输入信号在放大器电路的输入端产生升压的输入信号。 例如，升压电路可以包括耦合在输入缓冲器输入端子和放大器电路的输入端子之间的电容器，以及响应于控制信号将放大器电路的输入端子耦合到参考电压源的开关 。 检测器电路可操作以响应于输出信号的转变而产生脉冲，并且开关可以用于响应于脉冲将放大器电路的输入端耦合到参考电压源。