公开(公告)号：US07948272B2

公开(公告)日：2011-05-24

申请号：US10990412

申请日：2004-11-18

申请人： Dong-jin Lee ,  Jung-bae Lee ,  Kyu-hyoun Kim

发明人： Dong-jin Lee ,  Jung-bae Lee ,  Kyu-hyoun Kim

IPC分类号： H03K5/22

CPC分类号： H03K19/003

摘要： An input buffer which detects an input signal. The input buffer including an output node, a first buffer, and a second buffer. The first buffer may control the voltage level of the output node when the voltage level of a reference voltage signal is equal to a predetermined voltage level. The second buffer may control the voltage level of the output node in response to the input signal when the voltage level of the reference voltage signal is lower than the predetermined voltage level. The second buffer may maintain the output node at a first level. The second buffer may include an output control section and a level control unit. The output control section may receive the input signal and generate a level output signal at a second level. The level control section may generate a control signal which maintains the output node at the first level, in response to the level output signal when the voltage level of the reference voltage signal is lower than the predetermined voltage level of the first voltage and may intercept the control signal when the voltage level of the reference voltage signal is equal to the predetermined voltage level.

摘要翻译： 输入缓冲器，用于检测输入信号。 输入缓冲器包括输出节点，第一缓冲器和第二缓冲器。 当参考电压信号的电压电平等于预定电压电平时，第一缓冲器可以控制输出节点的电压电平。 当参考电压信号的电压电平低于预定电压电平时，第二缓冲器可以响应于输入信号来控制输出节点的电压电平。 第二缓冲器可以将输出节点维持在第一级。 第二缓冲器可以包括输出控制部分和电平控制单元。 输出控制部分可以接收输入信号并产生第二电平的电平输出信号。 当参考电压信号的电压电平低于第一电压的预定电压电平时，电平控制部分可以响应于电平输出信号而产生将输出节点维持在第一电平的控制信号，并且可以拦截 当参考电压信号的电压电平等于预定电压电平时，控制信号。

公开(公告)号：US20050116746A1

公开(公告)日：2005-06-02

申请号：US10990412

申请日：2004-11-18

申请人： Dong-jin Lee ,  Jung-bae Lee ,  Kyu-hyoun Kim

发明人： Dong-jin Lee ,  Jung-bae Lee ,  Kyu-hyoun Kim

IPC分类号： H03K19/0175 ,  H03K19/003 ,  H03B1/00

CPC分类号： H03K19/003

摘要： An input buffer which detects an input signal. The input buffer including an output node, a first buffer, and a second buffer. The first buffer may control the voltage level of the output node when the voltage level of a reference voltage signal is equal to a predetermined voltage level. The second buffer may control the voltage level of the output node in response to the input signal when the voltage level of the reference voltage signal is lower than the predetermined voltage level. The second buffer may maintain the output node at a first level. The second buffer may include an output control section and a level control unit. The output control section may receive the input signal and generate a level output signal at a second level. The level control section may generate a control signal which maintains the output node at the first level, in response to the level output signal when the voltage level of the reference voltage signal is lower than the predetermined voltage level of the first voltage and may intercept the control signal when the voltage level of the reference voltage signal is equal to the predetermined voltage level.

摘要翻译： 输入缓冲器，用于检测输入信号。 输入缓冲器包括输出节点，第一缓冲器和第二缓冲器。 当参考电压信号的电压电平等于预定电压电平时，第一缓冲器可以控制输出节点的电压电平。 当参考电压信号的电压电平低于预定电压电平时，第二缓冲器可以响应于输入信号来控制输出节点的电压电平。 第二缓冲器可以将输出节点维持在第一级。 第二缓冲器可以包括输出控制部分和电平控制单元。 输出控制部分可以接收输入信号并产生第二电平的电平输出信号。 当参考电压信号的电压电平低于第一电压的预定电压电平时，电平控制部分可以响应于电平输出信号而产生将输出节点维持在第一电平的控制信号，并且可以拦截 当参考电压信号的电压电平等于预定电压电平时，控制信号。

公开(公告)号：US07085336B2

公开(公告)日：2006-08-01

申请号：US09875364

申请日：2001-06-05

申请人： Jung-bae Lee ,  Kyu-hyoun Kim

发明人： Jung-bae Lee ,  Kyu-hyoun Kim

IPC分类号： H04L7/00

CPC分类号： H04L1/22 ,  H04L25/14

摘要： A signal transmission circuit and a method equalize differential delay characteristics of two signal transmission lines. A controllable delay unit is connected serially to the second line, so as to compensate by adding its internal delay. An auxiliary signal transmission line replicates the second transmission line, while it processes the input signal of the first. A controlling unit compares the output signal of the first transmission line and the of the auxiliary signal transmission line, and adjusts dynamically the internal delay of the controllable delay unit, to attain continuous synchronization. A data latch circuit synchronizes the delays of data paths by having one controllable delay units in each of the data paths.

摘要翻译： 信号传输电路和均衡两条信号传输线的差分延迟特性的方法。 可控延迟单元串联连接到第二线，以便通过增加其内部延迟来补偿。 辅助信号传输线在处理第一传输线的输入信号时复制第二传输线。 控制单元将第一传输线的输出信号与辅助信号传输线的输出信号进行比较，并动态地调整可控延迟单元的内部延迟，以获得连续同步。 数据锁存电路通过在每个数据路径中具有一个可控延迟单元来同步数据路径的延迟。

公开(公告)号：US06414517B1

公开(公告)日：2002-07-02

申请号：US09685266

申请日：2000-10-10

申请人： Kyu-hyoun Kim ,  Jung-bae Lee

发明人： Kyu-hyoun Kim ,  Jung-bae Lee

IPC分类号： H03K19094

CPC分类号： H04L25/028 ,  H04L25/0272

摘要： An input buffer includes an amplifier circuit, such as a differential amplifier circuit, inverting amplifier circuit or pull-up/pull-down amplifier circuit. A momentary boost circuit is coupled to an input buffer input terminal, an input terminal of the amplifier circuit, and an output terminal of the amplifier circuit, and is operative to generate a boosted input signal at the input terminal of the amplifier circuit from an input signal at an input buffer input terminal for an interval that is terminated responsive to an output signal at the output terminal of the amplifier circuit. The momentary boost circuit may include a detector circuit coupled to the output terminal of the amplifier circuit and operative to generate a control signal responsive to a transition of the output signal, and a boost circuit, coupled between the input buffer input terminal and the input terminal of the amplifier circuit and operatively associated with the detector circuit, that receives the input signal at the input buffer input terminal and generates the boosted input signal at the input terminal of the amplifier circuit from the received input signal responsive to the control signal. For example, the boost circuit may include a capacitor coupled between the input buffer input terminal and the input terminal of the amplifier circuit, and a switch that couples and decouples the input terminal of the amplifier circuit to a reference voltage source responsive to the control signal. The detector circuit may be operative to generate a pulse responsive to a transition of the output signal, and the switch may be operative to couple the input terminal of the amplifier circuit to the reference voltage source responsive to the pulse.

摘要翻译： 输入缓冲器包括诸如差分放大器电路，反相放大器电路或上拉/下拉放大器电路的放大器电路。 瞬时升压电路耦合到输入缓冲器输入端子，放大器电路的输入端子和放大器电路的输出端子，并且可操作以从放大器电路的输入端在输入端产生升压输入信号 在输入缓冲器输入端子处，响应于在放大器电路的输出端子处的输出信号而终止的间隔的信号。 瞬时升压电路可以包括耦合到放大器电路的输出端的检测器电路，并且可操作以响应于输出信号的转变而产生控制信号，以及耦合在输入缓冲器输入端和输入端之间的升压电路 并且与检测器电路可操作地相关联，其在输入缓冲器输入端子处接收输入信号，并且响应于控制信号从所接收的输入信号在放大器电路的输入端产生升压的输入信号。 例如，升压电路可以包括耦合在输入缓冲器输入端子和放大器电路的输入端子之间的电容器，以及响应于控制信号将放大器电路的输入端子耦合到参考电压源的开关 。 检测器电路可操作以响应于输出信号的转变而产生脉冲，并且开关可以用于响应于脉冲将放大器电路的输入端耦合到参考电压源。

公开(公告)号：US06466071B2

公开(公告)日：2002-10-15

申请号：US09826566

申请日：2001-04-05

申请人： Kyu-hyoun Kim ,  Jung-bae Lee

发明人： Kyu-hyoun Kim ,  Jung-bae Lee

IPC分类号： H03K3017

CPC分类号： H03K5/1565 ,  H03K5/133 ,  H03L7/0812 ,  H03L2207/12 ,  Y10S331/02

摘要： A signal is duty-cycle corrected by delaying the signal to generate a delayed version of the signal and generating an output signal that transitions from a first state to a second state responsive to a transition of the signal from the first state to the second state and a transition of the delayed version of the signal from the second state to the first state. The output signal transitions from the second state to the first state responsive to a transition of the signal from the second state to the first state and a transition of the delayed version of the signal from the first state to the second state.

摘要翻译： 通过延迟信号以产生信号的延迟版本并产生响应于信号从第一状态到第二状态的转变而从第一状态转变到第二状态的输出信号来对信号进行占空比校正， 将信号的延迟版本从第二状态转换到第一状态。 响应于信号从第二状态到第一状态的转变以及信号从第一状态到第二状态的延迟版本的转变，输出信号从第二状态转变到第一状态。

公开(公告)号：US08635487B2

公开(公告)日：2014-01-21

申请号：US12723843

申请日：2010-03-15

申请人： Kevin C. Gower ,  Kyu-hyoun Kim

发明人： Kevin C. Gower ,  Kyu-hyoun Kim

IPC分类号： H03M13/00 ,  G06F13/00 ,  G06F3/00 ,  G11C8/00

CPC分类号： G06F1/04 ,  G06F13/1694 ,  G11C7/1093 ,  G11C2207/2254

摘要： Methods and systems for calibrating parameters for communication between a controller and a memory device. A memory controller may be configured to calibrate one or more of the write latency and/or the latency window of a memory device such that a data signal and a data strobe signal are received by the memory device within the latency window of the memory device.

摘要翻译： 用于校准控制器和存储器件之间通信的参数的方法和系统。 存储器控制器可以被配置为校准存储器件的写延迟和/或等待时间窗口中的一个或多个，使得数据信号和数据选通信号在存储器件的延迟窗口内由存储器件接收。

公开(公告)号：US20130332680A1

公开(公告)日：2013-12-12

申请号：US13494280

申请日：2012-06-12

申请人： Paul W. Coteus ,  Kyu-hyoun Kim

发明人： Paul W. Coteus ,  Kyu-hyoun Kim

IPC分类号： G06F12/00

CPC分类号： G11C29/26 ,  G06F13/1684 ,  G06F13/1689 ,  G11C29/023 ,  G11C29/028 ,  G11C2029/2602

摘要： A method and circuit for implementing synchronized memory activities of multiple memory devices being accessed in parallel, and a design structure on which the subject circuit resides are provided. Each memory circuit generates an internal status signal for predefined internal memory activities and provides an output signal coupled to the multiple memory devices. Each memory circuit monitors the generated internal status signal and the output signal of at least one of the multiple memory devices, and responsive to the monitored signals generates a control signal for adjusting operation of its memory activities to synchronize memory activities of the memory devices.

摘要翻译： 一种用于实现并行访问的多个存储器件的同步存储器活动的方法和电路，以及设置有被摄体电路的设计结构。 每个存储器电路产生用于预定义的内部存储器活动的内部状态信号，并提供耦合到多个存储器件的输出信号。 每个存储器电路监视生成的内部状态信号和多个存储器件中的至少一个的输出信号，并且响应于所监视的信号产生用于调整其存储器活动的操作以控制存储器件的存储器活动的控制信号。

公开(公告)号：US08543753B2

公开(公告)日：2013-09-24

申请号：US13080799

申请日：2011-04-06

申请人： Daniel M. Dreps ,  Kyu-hyoun Kim ,  Michael A. Sorna ,  Glen A. Wiedemeier

发明人： Daniel M. Dreps ,  Kyu-hyoun Kim ,  Michael A. Sorna ,  Glen A. Wiedemeier

IPC分类号： G06F1/10 ,  G06F13/38

CPC分类号： G06F13/385 ,  G06F1/10 ,  G06F13/4072 ,  G11C7/1006 ,  G11C7/1066 ,  G11C7/1093

摘要： A multi-use physical (PHY) architecture that includes a PHY connection that includes one or more bit lines and that is communicatively coupled to a first processor. The PHY connection is configurable to carry signals between the first processor and a second processor, or between the first processor and a memory. The one or more bit lines are configured to carry signals bi-directionally at a first voltage when the PHY connection is configured to carry signals between the first processor and the memory. The one or more bit lines are configured to carry signals uni-directionally at a second voltage when the PHY connection is configured to carry signals between the first processor and the second processor. The second voltage is different than the first voltage.

摘要翻译： 一种多用途物理（PHY）架构，其包括包括一个或多个位线并且通信地耦合到第一处理器的PHY连接。 PHY连接可配置为在第一处理器和第二处理器之间或第一处理器和存储器之间传送信号。 一个或多个位线被配置为当PHY连接被配置为在第一处理器和存储器之间传送信号时以双向方式携带信号处于第一电压。 当PHY连接被配置为在第一处理器和第二处理器之间传送信号时，一个或多个位线被配置为以第二电压单向地传送信号。 第二电压不同于第一电压。

公开(公告)号：US08493801B2

公开(公告)日：2013-07-23

申请号：US13570430

申请日：2012-08-09

申请人： Daniel M. Dreps ,  Kevin C. Gower ,  Michael K. Kerr ,  Kyu-hyoun Kim ,  David W. Mann ,  James A. Mossman ,  Michael A. Sorna ,  Robert B. Tremaine ,  William M. Zevin

发明人： Daniel M. Dreps ,  Kevin C. Gower ,  Michael K. Kerr ,  Kyu-hyoun Kim ,  David W. Mann ,  James A. Mossman ,  Michael A. Sorna ,  Robert B. Tremaine ,  William M. Zevin

IPC分类号： G11C7/00

CPC分类号： G06F13/4243 ,  G06F13/1689 ,  G11C7/1051 ,  G11C7/1066 ,  G11C2207/2254

摘要： A method and apparatus for determining correct timing for receiving, in a host in a memory system, of a normal toggle transmitted by an addressed memory chip on a bidirectional data strobe. An offset in the data strobe is established, either by commanding the addressed memory chip, in a training period, to drive the data strobe to a known state, except during transmission of a normal toggle, or by providing a voltage offset between a true and a complement phase in the data strobe, or by providing a circuit bias in a differential receiver on the host the receives the data strobe. A series of read commands are transmitted by the host to the addressed memory chip, which responds by transmitting the normal toggle. Timing of reception of the normal toggle as received by the host chip is adjusted until the normal toggle is correctly received.

摘要翻译： 一种用于确定正确定时的方法和装置，用于在存储器系统中的主机中接收在双向数据选通信号上由寻址的存储器芯片发送的正常触发。 通过在训练期间命令寻址的存储器芯片来建立数据选通中的偏移量，以将数据选通驱动到已知状态，除了在正常触发的传输期间，或通过在真实和 数据选通中的补码相位，或通过在主机上的差分接收器中提供电路偏置来接收数据选通信号。 一系列读命令由主机发送到寻址的存储器芯片，通过发送普通切换进行响应。 调整由主机芯片接收到的正常切换的接收定时，直到正常接通正常。

公开(公告)号：US20120300564A1

公开(公告)日：2012-11-29

申请号：US13570430

申请日：2012-08-09

申请人： Daniel M. Dreps ,  Kevin C. Gower ,  Michael K. Kerr ,  Kyu-hyoun Kim ,  David W. Mann ,  James A. Mossman ,  Michael A. Sorna ,  Robert B. Tremaine ,  William M. Zevin

发明人： Daniel M. Dreps ,  Kevin C. Gower ,  Michael K. Kerr ,  Kyu-hyoun Kim ,  David W. Mann ,  James A. Mossman ,  Michael A. Sorna ,  Robert B. Tremaine ,  William M. Zevin

IPC分类号： G11C7/00

CPC分类号： G06F13/4243 ,  G06F13/1689 ,  G11C7/1051 ,  G11C7/1066 ,  G11C2207/2254

摘要： A method and apparatus for determining correct timing for receiving, in a host in a memory system, of a normal toggle transmitted by an addressed memory chip on a bidirectional data strobe. An offset in the data strobe is established, either by commanding the addressed memory chip, in a training period, to drive the data strobe to a known state, except during transmission of a normal toggle, or by providing a voltage offset between a true and a complement phase in the data strobe, or by providing a circuit bias in a differential receiver on the host the receives the data strobe. A series of read commands are transmitted by the host to the addressed memory chip, which responds by transmitting the normal toggle. Timing of reception of the normal toggle as received by the host chip is adjusted until the normal toggle is correctly received.

摘要翻译： 一种用于确定正确定时的方法和装置，用于在存储器系统中的主机中接收在双向数据选通信号上由寻址的存储器芯片发送的正常触发。 通过在训练期间命令寻址的存储器芯片来建立数据选通中的偏移量，以将数据选通驱动到已知状态，除了在正常触发的传输期间，或通过在真实和 数据选通中的补码相位，或通过在主机上的差分接收器中提供电路偏置来接收数据选通信号。 一系列读命令由主机发送到寻址的存储器芯片，通过发送普通切换进行响应。 调整由主机芯片接收到的正常切换的接收定时，直到正常接通正常。