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    Synchronous rectifier gate drive timing to compensate for transformer leakage inductance
    2.
    发明授权
    Synchronous rectifier gate drive timing to compensate for transformer leakage inductance 有权
    同步整流栅驱动定时补偿变压器漏电感

    公开(公告)号：US08358522B2

    公开(公告)日：2013-01-22

    申请号：US12836933

    申请日：2010-07-15

    Applicant: Paul W. Coteus ,  Andrew Ferencz

    Inventor： Paul W. Coteus ,  Andrew Ferencz

    IPC: H02M5/42

    CPC classification number: H02M3/33592 ,  H02M2001/0048 ,  Y02B70/1475 ,  Y02B70/1491

    Abstract: An apparatus for providing synchronous rectifier gate drive timing is described. The apparatus includes circuitry to receive a first signal. The apparatus also includes circuitry to generate a second signal by modifying the first signal to delay a transition from high to low for a non-zero overlap duration. An output to apply an inverse of the first signal as a gate drive timing of at least a first transistor and to apply the second signal as a gate drive timing of at least a second transistor, where the first transistor is a part of a primary side of a full-bridge synchronous rectifier and the second transistor is a part of a secondary side of the full-bridge synchronous rectifier is also included. The second signal and the inverse of the first signal are high during the overlap duration. Methods and program storage devices are also disclosed.

    Abstract translation: 描述了一种用于提供同步整流栅驱动定时的装置。 该装置包括用于接收第一信号的电路。 该装置还包括通过修改第一信号以在非零重叠持续时间内将从高转变为低的过渡来产生第二信号的电路。 用于将第一信号的反相作为至少第一晶体管的栅极驱动定时的输出，并施加第二信号作为至少第二晶体管的栅极驱动定时，其中第一晶体管是初级侧的一部分 的全桥同步整流器，而第二晶体管也是全桥同步整流二次侧的一部分。 第二信号和第一信号的反相在重叠期间是高的。 还公开了方法和程序存储装置。

    Through board stacking of multiple LGA-connected components
    5.
    发明授权
    Through board stacking of multiple LGA-connected components 有权
    通过板堆叠多个LGA连接的组件

    公开(公告)号：US08278745B2

    公开(公告)日：2012-10-02

    申请号：US12543104

    申请日：2009-08-18

    Applicant: Paul W. Coteus ,  Shawn A. Hall ,  Gareth G. Hougham ,  Alphonso P. Lanzetta ,  Rick A. Rand

    Inventor： Paul W. Coteus ,  Shawn A. Hall ,  Gareth G. Hougham ,  Alphonso P. Lanzetta ,  Rick A. Rand

    IPC: H01L23/52

    CPC classification number: H05K3/325 ,  H05K2201/0314 ,  H05K2201/10545 ,  H05K2201/10719 ,  H05K2201/2018

    Abstract: A package design is provided where a chip module is connected to a printed circuit board (PCB) via a land grid array (LGA) on the top surface of the PCB, and where a power supply is connected to the PCB via a second LGA on the bottom surface of the PCB. The stack of the chip module, power supply, and LGA is held in place and compressed with actuation hardware forming an adjustable frame. The package allows field replacibility of either the module, or the PS, and provides the shortest possible wiring distance from the PS to the module leading to higher performance.

    Abstract translation: 提供了一种封装设计，其中芯片模块通过PCB顶表面上的焊盘网格阵列（LGA）连接到印刷电路板（PCB），并且电源通过第二个LGA连接到PCB PCB的底面。 芯片模块，电源和LGA的堆叠被保持就位并用致动硬件压缩形成可调节的框架。 该封装允许模块或PS的现场可替代性，并提供从PS到模块的最短可能布线距离，从而实现更高的性能。

    MANAGING COHERENCE VIA PUT/GET WINDOWS
    9.
    发明申请
    MANAGING COHERENCE VIA PUT/GET WINDOWS 失效
    通过输入/获取窗口管理相关性

    公开(公告)号：US20110072219A1

    公开(公告)日：2011-03-24

    申请号：US12953770

    申请日：2010-11-24

    Applicant: Matthias A. Blumrich ,  Dong Chen ,  Paul W. Coteus ,  Alan G. Gara ,  Mark E. Giampapa ,  Phillip Heidelberger ,  Dirk Hoenicke ,  Martin Ohmacht

    Inventor： Matthias A. Blumrich ,  Dong Chen ,  Paul W. Coteus ,  Alan G. Gara ,  Mark E. Giampapa ,  Phillip Heidelberger ,  Dirk Hoenicke ,  Martin Ohmacht

    IPC: G06F12/08

    CPC classification number: H05K7/20836 ,  F24F11/77 ,  G06F9/52 ,  G06F9/526 ,  G06F15/17381 ,  G06F17/142 ,  G09G5/008 ,  H04L7/0338

    Abstract: A method and apparatus for managing coherence between two processors of a two processor node of a multi-processor computer system. Generally the present invention relates to a software algorithm that simplifies and significantly speeds the management of cache coherence in a message passing parallel computer, and to hardware apparatus that assists this cache coherence algorithm. The software algorithm uses the opening and closing of put/get windows to coordinate the activated required to achieve cache coherence. The hardware apparatus may be an extension to the hardware address decode, that creates, in the physical memory address space of the node, an area of virtual memory that (a) does not actually exist, and (b) is therefore able to respond instantly to read and write requests from the processing elements.

    Abstract translation: 一种用于管理多处理器计算机系统的两个处理器节点的两个处理器之间的相干性的方法和装置。 通常，本发明涉及一种软件算法，其简化并显着加速了传送并行计算机的消息中的高速缓存一致性的管理以及辅助该高速缓存一致性算法的硬件设备。 软件算法使用put / get窗口的打开和关闭来协调激活的所需要的，以实现缓存一致性。 硬件设备可以是硬件地址解码的扩展，其在节点的物理存储器地址空间中创建（a）实际不存在的虚拟存储器的区域，并且（b）因此能够立即响应 从处理元素读取和写入请求。

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