公开(公告)号：US20120266008A1

公开(公告)日：2012-10-18

申请号：US13085879

申请日：2011-04-13

Applicant: Paul W. Coteus ,  Alan Gara ,  Thomas M. Gooding ,  Rudolf A. Haring ,  Gerard V. Kopcsay ,  Thomas A. Liebsch ,  Don D. Reed

Inventor： Paul W. Coteus ,  Alan Gara ,  Thomas M. Gooding ,  Rudolf A. Haring ,  Gerard V. Kopcsay ,  Thomas A. Liebsch ,  Don D. Reed

IPC: G06F1/12

CPC classification number: G06F1/329 ,  G06F1/10 ,  G06F1/12 ,  G06F1/206 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/172 ,  Y02D10/24

Abstract: An apparatus, method and computer program product for automatically controlling power dissipation of a parallel computing system that includes a plurality of processors. A computing device issues a command to the parallel computing system. A clock pulse-width modulator encodes the command in a system clock signal to be distributed to the plurality of processors. The plurality of processors in the parallel computing system receive the system clock signal including the encoded command, and adjusts power dissipation according to the encoded command.

Abstract translation: 一种用于自动控制包括多个处理器的并行计算系统的功耗的装置，方法和计算机程序产品。 计算设备向并行计算系统发出命令。 时钟脉冲宽度调制器对系统时钟信号中的命令进行编码，以分配给多个处理器。 并行计算系统中的多个处理器接收包括编码命令的系统时钟信号，并根据编码命令调整功耗。

公开(公告)号：US07761687B2

公开(公告)日：2010-07-20

申请号：US11768905

申请日：2007-06-26

Applicant: Matthias A. Blumrich ,  Dong Chen ,  George Chiu ,  Thomas M. Cipolla ,  Paul W. Coteus ,  Alan G. Gara ,  Mark E. Giampapa ,  Shawn Hall ,  Rudolf A. Haring ,  Philip Heidelberger ,  Gerard V. Kopcsay ,  Martin Ohmacht ,  Valentina Salapura ,  Krishnan Sugavanam ,  Todd Takken

Inventor： Matthias A. Blumrich ,  Dong Chen ,  George Chiu ,  Thomas M. Cipolla ,  Paul W. Coteus ,  Alan G. Gara ,  Mark E. Giampapa ,  Shawn Hall ,  Rudolf A. Haring ,  Philip Heidelberger ,  Gerard V. Kopcsay ,  Martin Ohmacht ,  Valentina Salapura ,  Krishnan Sugavanam ,  Todd Takken

IPC: G06F15/173

CPC classification number: G06F15/17337

Abstract: A massively parallel supercomputer of petaOPS-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC) having up to four processing elements. The ASIC nodes are interconnected by multiple independent networks that optimally maximize the throughput of packet communications between nodes with minimal latency. The multiple networks may include three high-speed networks for parallel algorithm message passing including a Torus, collective network, and a Global Asynchronous network that provides global barrier and notification functions. These multiple independent networks may be collaboratively or independently utilized according to the needs or phases of an algorithm for optimizing algorithm processing performance. The use of a DMA engine is provided to facilitate message passing among the nodes without the expenditure of processing resources at the node.

Abstract translation: petaOPS规模的大规模并行超级计算机包括基于片上系统技术的节点架构，其中每个处理节点包括具有多达四个处理元件的单个专用集成电路（ASIC）。 ASIC节点通过多个独立网络互连，以最小的延迟最大化节点之间的数据包通信的吞吐量。 多个网络可以包括用于并行算法消息传递的三个高速网络，包括Torus，集合网络和提供全局障碍和通知功能的全球异步网络。 这些多个独立网络可以根据用于优化算法处理性能的算法的需求或阶段来协同或独立地利用。 提供DMA引擎的使用以促进节点之间的消息传递，而不需要节点处理资源。

公开(公告)号：US07405990B2

公开(公告)日：2008-07-29

申请号：US11872085

申请日：2007-10-15

Applicant: Arthur A. Bright ,  Paul G. Crumley ,  Marc B. Dombrowa ,  Steven M. Douskey ,  Rudolf A. Haring ,  Steven F. Oakland ,  Michael R. Ouellette ,  Scott A. Strissel

Inventor： Arthur A. Bright ,  Paul G. Crumley ,  Marc B. Dombrowa ,  Steven M. Douskey ,  Rudolf A. Haring ,  Steven F. Oakland ,  Michael R. Ouellette ,  Scott A. Strissel

IPC: G11C17/18 ,  G11C7/10 ,  G11C8/00 ,  H03K19/003 ,  H03K19/00

CPC classification number: G11C29/4401 ,  G11C29/802

Abstract: Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

公开(公告)号：US07397709B2

公开(公告)日：2008-07-08

申请号：US11872088

申请日：2007-10-15

Applicant: Arthur A. Bright ,  Paul G. Crumley ,  Marc B. Dombrowa ,  Steven M. Douskey ,  Rudolf A. Haring ,  Steven F. Oakland ,  Michael R. Ouellette ,  Scott A. Strissel

Inventor： Arthur A. Bright ,  Paul G. Crumley ,  Marc B. Dombrowa ,  Steven M. Douskey ,  Rudolf A. Haring ,  Steven F. Oakland ,  Michael R. Ouellette ,  Scott A. Strissel

IPC: G11C7/10 ,  G11C29/00 ,  G11C17/18 ,  H03K19/003 ,  G06F11/00

CPC classification number: G11C29/4401 ,  G11C29/802

Abstract: Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

Abstract translation: 公开了一种修复包括多个存储器阵列的类型的集成电路的方法，以及用于控制用于控制阵列的冗余逻辑的控制数据的保险丝盒。 该方法包括以下步骤：向集成电路提供控制数据选择器，用于将控制数据从保险丝盒传送到存储器阵列; 提供备用控制数据源，集成电路外部; 并将替代控制数据源连接到控制数据选择器。 该方法还包括在给定时间，通过控制数据选择器将备用控制数据从其源传递到存储器阵列以控制存储器阵列的冗余逻辑的步骤。

公开(公告)号：US08868975B2

公开(公告)日：2014-10-21

申请号：US13196459

申请日：2011-08-02

Applicant: Ralph E. Bellofatto ,  Steven M. Douskey ,  Rudolf A. Haring ,  Moyra K. McManus ,  Martin Ohmacht ,  Dietmar Schmunkamp ,  Krishnan Sugavanam ,  Bryan J. Weatherford

Inventor： Ralph E. Bellofatto ,  Steven M. Douskey ,  Rudolf A. Haring ,  Moyra K. McManus ,  Martin Ohmacht ,  Dietmar Schmunkamp ,  Krishnan Sugavanam ,  Bryan J. Weatherford

IPC: G06F11/00 ,  G06F11/22 ,  G06F11/20

CPC classification number: G06F11/2242 ,  G06F11/202

Abstract: A system and method for improving the yield rate of a multiprocessor semiconductor chip that includes primary processor cores and one or more redundant processor cores. A first tester conducts a first test on one or more processor cores, and encodes results of the first test in an on-chip non-volatile memory. A second tester conducts a second test on the processor cores, and encodes results of the second test in an external non-volatile storage device. An override bit of a multiplexer is set if a processor core fails the second test. In response to the override bit, the multiplexer selects a physical-to-logical mapping of processor IDs according to one of: the encoded results in the memory device or the encoded results in the external storage device. On-chip logic configures the processor cores according to the selected physical-to-logical mapping.

Abstract translation: 一种用于提高包括主处理器核心和一个或多个冗余处理器核心的多处理器半导体芯片的产率的系统和方法。 第一个测试人员对一个或多个处理器内核进行第一次测试，并在片上非易失性存储器中对第一次测试的结果进行编码。 第二个测试者对处理器核进行第二次测试，并将外部非易失性存储设备的第二次测试结果进行编码。 如果处理器核心故障第二次测试，则设置多路复用器的覆盖位。 响应于覆盖位，多路复用器根据以下之一选择处理器ID的物理到逻辑映射：存储器件中的编码结果或外部存储器件中的编码结果。 片上逻辑根据所选的物理到逻辑映射配置处理器内核。

公开(公告)号：US08595554B2

公开(公告)日：2013-11-26

申请号：US12774475

申请日：2010-05-05

Applicant: Ralph A. Bellofatto ,  Dong Chen ,  Paul W. Coteus ,  Noel A. Eisley ,  Alan Gara ,  Thomas M. Gooding ,  Rudolf A. Haring ,  Philip Heidelberger ,  Gerard V. Kopcsay ,  Thomas A. Liebsch ,  Martin Ohmacht ,  Don D. Reed ,  Robert M. Senger ,  Burkhard Steinmacher-Burow ,  Yutaka Sugawara

Inventor： Ralph A. Bellofatto ,  Dong Chen ,  Paul W. Coteus ,  Noel A. Eisley ,  Alan Gara ,  Thomas M. Gooding ,  Rudolf A. Haring ,  Philip Heidelberger ,  Gerard V. Kopcsay ,  Thomas A. Liebsch ,  Martin Ohmacht ,  Don D. Reed ,  Robert M. Senger ,  Burkhard Steinmacher-Burow ,  Yutaka Sugawara

IPC: G06F11/00

CPC classification number: G06F1/10 ,  G06F11/2242

Abstract: Fixing a problem is usually greatly aided if the problem is reproducible. To ensure reproducibility of a multiprocessor system, the following aspects are proposed: a deterministic system start state, a single system clock, phase alignment of clocks in the system, system-wide synchronization events, reproducible execution of system components, deterministic chip interfaces, zero-impact communication with the system, precise stop of the system and a scan of the system state.

Abstract translation: 如果问题是可重现的，通常会大大帮助解决问题。 为了确保多处理器系统的可重复性，提出了以下方面：确定性系统启动状态，单个系统时钟，系统中的时钟相位对齐，全系统同步事件，系统组件的可重复执行，确定性芯片接口，零 - 与系统进行通信，精确地停止系统并扫描系统状态。

公开(公告)号：US08412974B2

公开(公告)日：2013-04-02

申请号：US12696764

申请日：2010-01-29

Applicant: Dong Chen ,  Matthew R. Ellavsky ,  Ross L. Franke ,  Alan Gara ,  Thomas M. Gooding ,  Rudolf A. Haring ,  Mark J. Jeanson ,  Gerard V. Kopcsay ,  Thomas A. Liebsch ,  Daniel Littrell ,  Martin Ohmacht ,  Don D. Reed ,  Brandon E. Schenck ,  Richard A. Swetz

Inventor： Dong Chen ,  Matthew R. Ellavsky ,  Ross L. Franke ,  Alan Gara ,  Thomas M. Gooding ,  Rudolf A. Haring ,  Mark J. Jeanson ,  Gerard V. Kopcsay ,  Thomas A. Liebsch ,  Daniel Littrell ,  Martin Ohmacht ,  Don D. Reed ,  Brandon E. Schenck ,  Richard A. Swetz

IPC: G06F1/04 ,  G06F1/12 ,  G06F15/16

CPC classification number: G06F1/08 ,  G06F1/10

Abstract: A circuit generates a global clock signal with a pulse width modification to synchronize processors in a parallel computing system. The circuit may include a hardware module and a clock splitter. The hardware module may generate a clock signal and performs a pulse width modification on the clock signal. The pulse width modification changes a pulse width within a clock period in the clock signal. The clock splitter may distribute the pulse width modified clock signal to a plurality of processors in the parallel computing system.

Abstract translation: 电路产生具有脉冲宽度修改的全局时钟信号，以使并行计算系统中的处理器同步。 电路可以包括硬件模块和时钟分离器。 硬件模块可以产生时钟信号并对时钟信号进行脉冲宽度修改。 脉冲宽度修改在时钟信号的时钟周期内改变脉冲宽度。 时钟分配器可以将脉冲宽度修改的时钟信号分配给并行计算系统中的多个处理器。

公开(公告)号：US08140925B2

公开(公告)日：2012-03-20

申请号：US11768791

申请日：2007-06-26

Applicant: Ralph E. Bellofatto ,  Matthew R. Ellavsky ,  Alan G. Gara ,  Mark E. Giampapa ,  Thomas M. Gooding ,  Rudolf A. Haring ,  Lance G. Hehenberger ,  Martin Ohmacht

Inventor： Ralph E. Bellofatto ,  Matthew R. Ellavsky ,  Alan G. Gara ,  Mark E. Giampapa ,  Thomas M. Gooding ,  Rudolf A. Haring ,  Lance G. Hehenberger ,  Martin Ohmacht

IPC: G01R31/28 ,  G06F1/12

CPC classification number: G06F11/2236

Abstract: An apparatus and method for evaluating a state of an electronic or integrated circuit (IC), each IC including one or more processor elements for controlling operations of IC sub-units, and each the IC supporting multiple frequency clock domains. The method comprises: generating a synchronized set of enable signals in correspondence with one or more IC sub-units for starting operation of one or more IC sub-units according to a determined timing configuration; counting, in response to one signal of the synchronized set of enable signals, a number of main processor IC clock cycles; and, upon attaining a desired clock cycle number, generating a stop signal for each unique frequency clock domain to synchronously stop a functional clock for each respective frequency clock domain; and, upon synchronously stopping all on-chip functional clocks on all frequency clock domains in a deterministic fashion, scanning out data values at a desired IC chip state. The apparatus and methodology enables construction of a cycle-by-cycle view of any part of the state of a running IC chip, using a combination of on-chip circuitry and software.

Abstract translation: 一种用于评估电子或集成电路（IC）的状态的装置和方法，每个IC包括用于控制IC子单元的操作的一个或多个处理器元件，以及每个支持多个时钟域的IC。 该方法包括：根据确定的定时配置，产生与一个或多个IC子单元相对应的用于开始一个或多个IC子单元的操作的同步的使能信号组; 计数，响应于同步的一组使能信号的一个信号，多个主处理器IC时钟周期; 并且在获得期望的时钟周期数时，产生用于每个唯一频率时钟域的停止信号以同步地停止每个相应频率时钟域的功能时钟; 并且在确定性地同时停止所有频率时钟域上的所有片上功能时钟时，以期望的IC芯片状态扫描数据值。 该装置和方法使得能够使用片上电路和软件的组合来构建运行中的IC芯片的状态的任何部分的逐周期视图。

公开(公告)号：US20090006808A1

公开(公告)日：2009-01-01

申请号：US11768905

申请日：2007-06-26

Applicant: Matthias A. Blumrich ,  Dong Chen ,  George Chiu ,  Thomas M. Cipolla ,  Paul W. Coteus ,  Alan G. Gara ,  Mark E. Giampapa ,  Shawn Hall ,  Rudolf A. Haring ,  Philip Heidelberger ,  Gerard V. Kopcsay ,  Martin Ohmacht ,  Valentina Salapura ,  Krishnan Sugavanam ,  Todd Takken

Inventor： Matthias A. Blumrich ,  Dong Chen ,  George Chiu ,  Thomas M. Cipolla ,  Paul W. Coteus ,  Alan G. Gara ,  Mark E. Giampapa ,  Shawn Hall ,  Rudolf A. Haring ,  Philip Heidelberger ,  Gerard V. Kopcsay ,  Martin Ohmacht ,  Valentina Salapura ,  Krishnan Sugavanam ,  Todd Takken

IPC: G06F15/80 ,  G06F9/06

CPC classification number: G06F15/17337

Abstract: A novel massively parallel supercomputer of petaOPS-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC) having up to four processing elements. The ASIC nodes are interconnected by multiple independent networks that optimally maximize the throughput of packet communications between nodes with minimal latency. The multiple networks may include three high-speed networks for parallel algorithm message passing including a Torus, collective network, and a Global Asynchronous network that provides global barrier and notification functions. These multiple independent networks may be collaboratively or independently utilized according to the needs or phases of an algorithm for optimizing algorithm processing performance. Novel use of a DMA engine is provided to facilitate message passing among the nodes without the expenditure of processing resources at the node.

Abstract translation: petaOPS规模的一种新型大规模并行超级计算机包括基于片上系统技术的节点架构，其中每个处理节点包括具有多达四个处理元件的单个专用集成电路（ASIC）。 ASIC节点通过多个独立网络互连，以最小的延迟最大化节点之间的数据包通信的吞吐量。 多个网络可以包括用于并行算法消息传递的三个高速网络，包括Torus，集合网络和提供全局障碍和通知功能的全球异步网络。 这些多个独立网络可以根据用于优化算法处理性能的算法的需求或阶段来协同或独立地利用。 提供了新的使用DMA引擎来促进节点之间的消息传递，而不需要节点处理资源。

公开(公告)号：US07310278B2

公开(公告)日：2007-12-18

申请号：US11418052

申请日：2006-05-04

Applicant: Arthur A. Bright ,  Paul G. Crumley ,  Marc B. Dombrowa ,  Steven M. Douskey ,  Rudolf A. Haring ,  Steven F. Oakland ,  Michael R. Ouellette ,  Scott A. Strissel

Inventor： Arthur A. Bright ,  Paul G. Crumley ,  Marc B. Dombrowa ,  Steven M. Douskey ,  Rudolf A. Haring ,  Steven F. Oakland ,  Michael R. Ouellette ,  Scott A. Strissel

IPC: G11C29/00 ,  G11C7/10 ,  G11C17/18 ,  H03K19/00

CPC classification number: G11C29/4401 ,  G11C29/802

Abstract: Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

Abstract translation: 公开了一种修复包括多个存储器阵列的类型的集成电路的方法，以及用于控制用于控制阵列的冗余逻辑的控制数据的保险丝盒。 该方法包括以下步骤：向集成电路提供控制数据选择器，用于将控制数据从保险丝盒传送到存储器阵列; 提供备用控制数据源，集成电路外部; 并将替代控制数据源连接到控制数据选择器。 该方法还包括在给定时间，通过控制数据选择器将备用控制数据从其源传递到存储器阵列以控制存储器阵列的冗余逻辑的步骤。