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    Training shoe for soccer
    1.
    发明授权
    Training shoe for soccer 失效
    足球训练鞋

    公开(公告)号：US06808462B2

    公开(公告)日：2004-10-26

    申请号：US10179501

    申请日：2002-06-25

    Applicant: Gregory P. Snyder ,  Matthew R. Ellavsky ,  Richard S. Little ,  Michael Nordquist

    Inventor： Gregory P. Snyder ,  Matthew R. Ellavsky ,  Richard S. Little ,  Michael Nordquist

    IPC: A63B6900

    CPC classification number: G09B19/0038 ,  A43B3/00 ,  A43B3/0005 ,  A43B3/0021 ,  A43B5/02 ,  A63B69/002 ,  A63B2071/0625 ,  A63B2071/0627

    Abstract: A training shoe for soccer includes a pressure-responsive sensor mounted with respect to a soccer shoe at a selected location, for example at the instep or along the laces at the top of the shoe. When a soccer ball is kicked at the selected location, the sensor provides an electrical signal to a microprocessor, causing selection logic in the microprocessor to choose one of several control words. The selected control word is provided to a voice playback circuit to select one of several digital data sets, each set corresponding to a different sound. The playback circuit provides an analog electrical control signal to a speaker, thereby generating a selected sound corresponding to the selected digital data set. System components can be mounted permanently to a shoe, or to a cover or strap arrangement releasably mounted to the shoe.

    Abstract translation: 用于足球的训练鞋包括在选定位置处相对于足球鞋安装的压力响应传感器，例如在脚背或鞋的顶部的鞋带。 当足球在所选择的位置踢球时，传感器向微处理器提供电信号，使得微处理器中的选择逻辑选择几个控制字中的一个。 所选择的控制字被提供给语音重放电路，以选择对应于不同声音的多个数字数据集中的一个。 播放电路向扬声器提供模拟电气控制信号，从而产生对应于所选择的数字数据集的选定声音。 系统部件可以永久地安装在鞋子上，或者可拆卸地安装在鞋子上的盖子或带子装置上。

    IIMPLEMENTING Z DIRECTIONAL MACRO PORT ASSIGNMENT
    2.
    发明申请
    IIMPLEMENTING Z DIRECTIONAL MACRO PORT ASSIGNMENT 失效
    取消Z方向广域网端口分配

    公开(公告)号：US20130042214A1

    公开(公告)日：2013-02-14

    申请号：US13208046

    申请日：2011-08-11

    Applicant: Matthew R. Ellavsky ,  Sean T. Evans ,  Timothy D. Helvey ,  Phillip P. Normand ,  Jason L. Van Vreede ,  Bradley C. White

    Inventor： Matthew R. Ellavsky ,  Sean T. Evans ,  Timothy D. Helvey ,  Phillip P. Normand ,  Jason L. Van Vreede ,  Bradley C. White

    IPC: G06F9/45

    CPC classification number: G06F17/5045 ,  G06F17/5077 ,  G06F2217/66

    Abstract: A method, system and computer program product are provided for implementing an enhanced Z-directional macro port assignment or three-dimensional port creation for random logic macros of heterogeneous hierarchical integrated circuit chips. An initial port placement is provided on a layer for a macro. The initial port placement is expanded to provide a three-dimensional port shape including a plurality of metal layers along a z-axis. Wire routing of each of the macro level and a chip top level is defined within the expanded three-dimensional port shape. Each unnecessary metal layer of the expanded three-dimensional port shape is removed, providing a final three-dimensional port shape.

    Abstract translation: 提供了一种方法，系统和计算机程序产品，用于实现用于异构分层集成电路芯片的随机逻辑宏的增强的Z方向宏端口分配或三维端口创建。 在宏的层上提供初始端口布局。 初始端口放置被扩展以提供包括沿z轴的多个金属层的三维端口形状。 在扩展的三维端口形状内定义每个宏级和芯片顶级的布线。 扩大的三维端口形状的每个不必要的金属层被去除，提供最终的三维端口形状。

    Radiation Tolerance by Clock Signal Interleaving
    3.
    发明申请
    Radiation Tolerance by Clock Signal Interleaving 失效
    通过时钟信号交错的辐射公差

    公开(公告)号：US20090241073A1

    公开(公告)日：2009-09-24

    申请号：US12051002

    申请日：2008-03-19

    Applicant: Matthew R. Ellavsky ,  Aj KleinOsowski ,  Scott M. Willenborg

    Inventor： Matthew R. Ellavsky ,  Aj KleinOsowski ,  Scott M. Willenborg

    IPC: G06F17/50

    CPC classification number: G06F17/505 ,  G06F2217/62

    Abstract: A method for designing integrated circuits uses clock signal interleaving to reduce the likelihood of a soft error arising from an upset in a clock distribution network. At least two circuits in a circuit description are identified as being sensitive to radiation, and different clock distribution nodes are assigned to the two circuits. Several exemplary implementations are disclosed. The second circuit may be a redundant replica of the first circuit, such as a reset circuit. The first and second circuits may be components of a modular redundant circuit such as a triple modular redundancy flip-flop. The first circuit may include a set of data bits for an entry of a storage array such as a register or memory array, and the second circuit may include a set of check bits associated with the entry.

    Abstract translation: 一种设计集成电路的方法使用时钟信号交织来减少由时钟分配网络中的不适引起的软错误的可能性。 电路描述中的至少两个电路被识别为对辐射敏感，并且不同的时钟分配节点被分配给两个电路。 公开了几个示例性实现。 第二电路可以是第一电路的冗余复制品，例如复位电路。 第一和第二电路可以是模块化冗余电路的组件，例如三模块冗余触发器。 第一电路可以包括用于诸如寄存器或存储器阵列的存储阵列的入口的一组数据位，并且第二电路可以包括与该条目相关联的一组校验位。

    Implementing Z directional macro port assignment
    4.
    发明授权
    Implementing Z directional macro port assignment 失效
    实现Z方向宏端口分配

    公开(公告)号：US08448121B2

    公开(公告)日：2013-05-21

    申请号：US13208046

    申请日：2011-08-11

    Applicant: Matthew R. Ellavsky ,  Sean T. Evans ,  Timothy D. Helvey ,  Phillip P. Normand ,  Jason L. Van Vreede ,  Bradley C. White

    Inventor： Matthew R. Ellavsky ,  Sean T. Evans ,  Timothy D. Helvey ,  Phillip P. Normand ,  Jason L. Van Vreede ,  Bradley C. White

    IPC: G06F17/50

    CPC classification number: G06F17/5045 ,  G06F17/5077 ,  G06F2217/66

    Abstract: A method, system and computer program product are provided for implementing an enhanced Z-directional macro port assignment or three-dimensional port creation for random logic macros of heterogeneous hierarchical integrated circuit chips. An initial port placement is provided on a layer for a macro. The initial port placement is expanded to provide a three-dimensional port shape including a plurality of metal layers along a z-axis. Wire routing of each of the macro level and a chip top level is defined within the expanded three-dimensional port shape. Each unnecessary metal layer of the expanded three-dimensional port shape is removed, providing a final three-dimensional port shape.

    Abstract translation: 提供了一种方法，系统和计算机程序产品，用于实现用于异构分层集成电路芯片的随机逻辑宏的增强的Z方向宏端口分配或三维端口创建。 在宏的层上提供初始端口布局。 初始端口放置被扩展以提供包括沿z轴的多个金属层的三维端口形状。 在扩展的三维端口形状内定义每个宏级和芯片顶级的布线。 扩大的三维端口形状的每个不必要的金属层被去除，提供最终的三维端口形状。

    CHANGING THE LOCATION OF A BUFFER BAY IN A NETLIST
    8.
    发明申请
    CHANGING THE LOCATION OF A BUFFER BAY IN A NETLIST 失效
    更改缓存器在网络列表中的位置

    公开(公告)号：US20120290995A1

    公开(公告)日：2012-11-15

    申请号：US13106005

    申请日：2011-05-12

    Applicant: Matthew R. Ellavsky ,  Sean T. Evans ,  Timothy D. Helvey ,  Phillip P. Normand ,  Jason L. Van Vreede ,  Bradley C. White

    Inventor： Matthew R. Ellavsky ,  Sean T. Evans ,  Timothy D. Helvey ,  Phillip P. Normand ,  Jason L. Van Vreede ,  Bradley C. White

    IPC: G06F17/50

    CPC classification number: G06F17/5072 ,  G06F17/505 ,  G06F17/5068

    Abstract: In an embodiment, a buffer bay is represented with a moveable object that has a location within a unit in a netlist. The location of the moveable object that represents the buffer bay is changed to a new location in the netlist if changing the location improves placement within the unit. In an embodiment, a net weight of a net that connects the moveable object to an artificial pin is considered in determining whether to change the location to the new location. In an embodiment a bounding area that encompasses the location is considered in determining whether to change the location to the new location.

    Abstract translation: 在一个实施例中，缓冲器托架由可移动对象表示，该可移动对象在网表中具有单位内的位置。 表示缓冲区的可移动对象的位置将更改为网络列表中的新位置，如果更改位置可改善单元中的位置。 在一个实施例中，在确定是否将位置改变到新位置时，考虑将可移动物体连接到人造针的网的净重。 在一个实施例中，在确定是否将位置改变到新位置时考虑包围该位置的边界区域。

    Method and apparatus to debug an integrated circuit chip via synchronous clock stop and scan
    9.
    发明授权
    Method and apparatus to debug an integrated circuit chip via synchronous clock stop and scan 失效
    通过同步时钟停止和扫描来调试集成电路芯片的方法和装置

    公开(公告)号：US08140925B2

    公开(公告)日：2012-03-20

    申请号：US11768791

    申请日：2007-06-26

    Applicant: Ralph E. Bellofatto ,  Matthew R. Ellavsky ,  Alan G. Gara ,  Mark E. Giampapa ,  Thomas M. Gooding ,  Rudolf A. Haring ,  Lance G. Hehenberger ,  Martin Ohmacht

    Inventor： Ralph E. Bellofatto ,  Matthew R. Ellavsky ,  Alan G. Gara ,  Mark E. Giampapa ,  Thomas M. Gooding ,  Rudolf A. Haring ,  Lance G. Hehenberger ,  Martin Ohmacht

    IPC: G01R31/28 ,  G06F1/12

    CPC classification number: G06F11/2236

    Abstract: An apparatus and method for evaluating a state of an electronic or integrated circuit (IC), each IC including one or more processor elements for controlling operations of IC sub-units, and each the IC supporting multiple frequency clock domains. The method comprises: generating a synchronized set of enable signals in correspondence with one or more IC sub-units for starting operation of one or more IC sub-units according to a determined timing configuration; counting, in response to one signal of the synchronized set of enable signals, a number of main processor IC clock cycles; and, upon attaining a desired clock cycle number, generating a stop signal for each unique frequency clock domain to synchronously stop a functional clock for each respective frequency clock domain; and, upon synchronously stopping all on-chip functional clocks on all frequency clock domains in a deterministic fashion, scanning out data values at a desired IC chip state. The apparatus and methodology enables construction of a cycle-by-cycle view of any part of the state of a running IC chip, using a combination of on-chip circuitry and software.

    Abstract translation: 一种用于评估电子或集成电路（IC）的状态的装置和方法，每个IC包括用于控制IC子单元的操作的一个或多个处理器元件，以及每个支持多个时钟域的IC。 该方法包括：根据确定的定时配置，产生与一个或多个IC子单元相对应的用于开始一个或多个IC子单元的操作的同步的使能信号组; 计数，响应于同步的一组使能信号的一个信号，多个主处理器IC时钟周期; 并且在获得期望的时钟周期数时，产生用于每个唯一频率时钟域的停止信号以同步地停止每个相应频率时钟域的功能时钟; 并且在确定性地同时停止所有频率时钟域上的所有片上功能时钟时，以期望的IC芯片状态扫描数据值。 该装置和方法使得能够使用片上电路和软件的组合来构建运行中的IC芯片的状态的任何部分的逐周期视图。

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