公开(公告)号：US09632778B2

公开(公告)日：2017-04-25

申请号：US13569363

申请日：2012-08-08

申请人： Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Jaime H. Moreno ,  Ravi Nair ,  Daniel A. Prener

发明人： Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Jaime H. Moreno ,  Ravi Nair ,  Daniel A. Prener

IPC分类号： G06F9/30

CPC分类号： G06F9/30043 ,  G06F9/30036

摘要： Embodiments relate to packed loading and storing of data. An aspect includes a system for packed loading and storing of distributed data. The system includes memory and a processing element configured to communicate with the memory. The processing element is configured to perform a method including fetching and decoding an instruction for execution by the processing element. A plurality of individually addressable data elements is gathered from non-contiguous locations in the memory which are narrower than a nominal width of register file elements in the processing element based on the instruction. The processing element packs and loads the data elements into register file elements of a register file entry based on the instruction, such that at least two of the data elements gathered from the non-contiguous locations in the memory are packed and loaded into a single register file element of the register file entry.

公开(公告)号：US09575756B2

公开(公告)日：2017-02-21

申请号：US13569349

申请日：2012-08-08

申请人： Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair

发明人： Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F15/80 ,  G11C7/10 ,  G11C8/12

CPC分类号： G06F9/30036 ,  G06F9/30018 ,  G06F9/3879 ,  G06F9/3887 ,  G06F15/8084 ,  G11C7/1006 ,  G11C8/12

摘要： Embodiments relate to vector processor predication in an active memory device. An aspect includes a system for vector processor predication in an active memory device. The system includes memory in the active memory device and a processing element in the active memory device. The processing element is configured to perform a method including decoding an instruction with a plurality of sub-instructions to execute in parallel. One or more mask bits are accessed from a vector mask register in the processing element. The one or more mask bits are applied by the processing element to predicate operation of a unit in the processing element associated with at least one of the sub-instructions.

摘要翻译： 实施例涉及有源存储器件中的矢量处理器预测。 一个方面包括用于有源存储器设备中的向量处理器预测的系统。 该系统包括有源存储器设备中的存储器和有源存储器设备中的处理元件。 处理单元被配置为执行包括用多个子指令解码指令并行执行的方法。 一个或多个掩码位从处理元件中的向量掩码寄存器访问。 一个或多个掩码位由处理元件应用于与至少一个子指令相关联的处理元件中的单元的谓词操作。

公开(公告)号：US09569211B2

公开(公告)日：2017-02-14

申请号：US13566129

申请日：2012-08-03

申请人： Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair

发明人： Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F15/80 ,  G11C7/10 ,  G11C8/12

CPC分类号： G06F9/30036 ,  G06F9/30018 ,  G06F9/3879 ,  G06F9/3887 ,  G06F15/8084 ,  G11C7/1006 ,  G11C8/12

摘要： Embodiments relate to vector processor predication in an active memory device. An aspect includes a method for vector processor predication in an active memory device that includes memory and a processing element. The method includes decoding, in the processing element, an instruction including a plurality of sub-instructions to execute in parallel. One or more mask bits are accessed from a vector mask register in the processing element. The one or more mask bits are applied by the processing element to predicate operation of a unit in the processing element associated with at least one of the sub-instructions.

摘要翻译： 实施例涉及有源存储器件中的矢量处理器预测。 一个方面包括一种用于包括存储器和处理元件的有源存储器件中的向量处理器预测的方法。 该方法包括在处理元件中解码包括并行执行的多个子指令的指令。 一个或多个掩码位从处理元件中的向量掩码寄存器访问。 一个或多个掩码位由处理元件应用于与至少一个子指令相关联的处理元件中的单元的谓词操作。

公开(公告)号：US20140040601A1

公开(公告)日：2014-02-06

申请号：US13566129

申请日：2012-08-03

申请人： Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair

发明人： Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair

IPC分类号： G06F9/30

CPC分类号： G06F9/30036 ,  G06F9/30018 ,  G06F9/3879 ,  G06F9/3887 ,  G06F15/8084 ,  G11C7/1006 ,  G11C8/12

摘要： Embodiments relate to vector processor predication in an active memory device. An aspect includes a method for vector processor predication in an active memory device that includes memory and a processing element. The method includes decoding, in the processing element, an instruction including a plurality of sub-instructions to execute in parallel. One or more mask bits are accessed from a vector mask register in the processing element. The one or more mask bits are applied by the processing element to predicate operation of a unit in the processing element associated with at least one of the sub-instructions.

摘要翻译： 实施例涉及有源存储器件中的矢量处理器预测。 一个方面包括一种用于包括存储器和处理元件的有源存储器件中的向量处理器预测的方法。 该方法包括在处理元件中解码包括并行执行的多个子指令的指令。 一个或多个掩码位从处理元件中的向量掩码寄存器访问。 一个或多个掩码位由处理元件应用于与至少一个子指令相关联的处理元件中的单元的谓词操作。

公开(公告)号：US20100095087A1

公开(公告)日：2010-04-15

申请号：US12250584

申请日：2008-10-14

申请人： Alexandre E. Eichenberger ,  Bruce M. Fleischer ,  Michael K. Gschwind

发明人： Alexandre E. Eichenberger ,  Bruce M. Fleischer ,  Michael K. Gschwind

IPC分类号： G06F9/06

CPC分类号： G06F9/30036 ,  G06F7/76 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/3887

摘要： Mechanisms are provided for dynamic data driven alignment and data formatting in a floating point SIMD architecture. At least two operand inputs are input to a permute unit of a processor. Each operand input contains at least one floating point value upon which a permute operation is to be performed by the permute unit. A control vector input, having a plurality of floating point values that together constitute the control vector input, is input to the permute unit of the processor for controlling the permute operation of the permute unit. The permute unit performs a permute operation on the at least two operand inputs according to a permutation pattern specified by the plurality of floating point values that constitute the control vector input. Moreover, a result output of the permute operation is output from the permute unit to a result vector register of the processor.

摘要翻译： 为浮点SIMD架构提供动态数据驱动对齐和数据格式化的机制。 至少两个操作数输入被输入到处理器的置换单元。 每个操作数输入包含至少一个浮点值，在该浮点值上由置换单元执行置换操作。 具有一起构成控制向量输入的多个浮点值的控制矢量输入被输入到处理器的置换单元，用于控制置换单元的置换操作。 置换单元根据由构成控制向量输入的多个浮点值指定的置换模式对至少两个操作数输入执行置换操作。 此外，置换操作的结果输出从处理单元输出到处理器的结果向量寄存器。

公开(公告)号：US20100095086A1

公开(公告)日：2010-04-15

申请号：US12250599

申请日：2008-10-14

申请人： Alexandre E. Eichenberger ,  Bruce M. Fleischer ,  Michael K. Gschwind

发明人： Alexandre E. Eichenberger ,  Bruce M. Fleischer ,  Michael K. Gschwind

IPC分类号： G06F15/76 ,  G06F9/30

CPC分类号： G06F9/30032 ,  G06F9/30025 ,  G06F9/30036 ,  G06F9/3887

摘要： Mechanisms for aligning enhanced precision vectors based on reduced precision data values are provided. At least one data value, having a first precision type, is received for storing in a vector register. The vector register stores data as a vector having a plurality of vector elements. The first precision type is modified to have a second precision type different in precision than the first precision type to thereby generate at least one modified data value. The at least one modified data value is stored in at least one vector element of the plurality of vector elements. An alignment of the at least one modified data value is determined relative to a boundary of a vector element of the vector register. An alignment operation to re-align the at least one modified data value based on the boundary of the vector element of the vector register is performed.

摘要翻译： 提供了基于减少的精度数据值对准增强精度向量的机制。 接收具有第一精度类型的至少一个数据值以存储在向量寄存器中。 向量寄存器将数据存储为具有多个向量元素的向量。 第一精度类型被修改为具有与第一精度类型不同的第二精度类型，从而生成至少一个修改的数据值。 所述至少一个修改的数据值存储在所述多个向量元素的至少一个向量元素中。 相对于向量寄存器的向量元素的边界确定至少一个经修改的数据值的对齐。 执行基于向量寄存器的向量元素的边界来重新对准至少一个修改的数据值的对准操作。

公开(公告)号：US20070294330A1

公开(公告)日：2007-12-20

申请号：US11425185

申请日：2006-06-20

申请人： Daniel Lipetz ,  Bruce M. Fleischer ,  Eric M. Schwarz

发明人： Daniel Lipetz ,  Bruce M. Fleischer ,  Eric M. Schwarz

IPC分类号： G06F7/38

CPC分类号： G06F7/72 ,  G06F7/727

摘要： Systems, methods and computer program products for providing a combined moduli-9 and 3 residue generator. The methods include receiving a number in binary coded decimal (BCD) or binary format. A modulus-9 residue of the number is calculated. The modulus-9 residue that is calculated includes a modulus-3 residue of the number. The modulis-3 residue of the number is output. If the number is in BCD format, then the modulus-9 residue of the number is output.

摘要翻译： 用于提供组合模块9和3残留发生器的系统，方法和计算机程序产品。 这些方法包括接收二进制编码十进制（BCD）或二进制格式的数字。 计算该数的9个模数。 计算出的模数为9的残差包括该数目的3的残基。 输出的模数3个残差。 如果数字为BCD格式，则输出该数字的9个模数。

公开(公告)号：US5191240A

公开(公告)日：1993-03-02

申请号：US710592

申请日：1991-06-05

申请人： Bruce M. Fleischer

发明人： Bruce M. Fleischer

IPC分类号： H01L21/822 ,  H01L21/8249 ,  H01L27/04 ,  H01L27/06 ,  H03K19/013 ,  H03K19/08 ,  H03K19/0944

CPC分类号： H03K19/0136 ,  H03K19/09448

摘要： A BiCMOS driver circuit with an improved low output level which is closer to ground than in prior art circuits, both at full speed and with a static (resistive) load. The driver circuit incorporates a gated diode pull-down with a lower voltage drop than in prior art driver circuits, in which a bipolar output transistor remains on for output voltages down to about 0.3V. The voltage drop of the gated diode is set by device size ratios to be less than 0.5V without driving the output transistor into hard saturation. In the circuit, a gated diode pull-down NPN transistor is coupled between an output terminal and ground. A first CMOS transistor pair is coupled between the output terminal and the base of the pull-down NPN transistor, and a second CMOS transistor pair is coupled between the output terminal and the power supply V.sub.DD. The circuit has improved low output level and high-to-low transitions. The circuit has particular applications to many types of logic gates, for example in NAND gates, NOR gates, and inverters, as are used extensively in static or dynamic random access memory logic circuits. Although the disclosed embodiments herein are for NAND gates, one skilled in the art could readily implement the teachings of the present invention in other logic circuits and gates, such as NOR gates and inverters with minor changes in the circuitry.

公开(公告)号：US09575753B2

公开(公告)日：2017-02-21

申请号：US13420699

申请日：2012-03-15

申请人： Alexandre E. Eichenberger ,  Bruce M. Fleischer

发明人： Alexandre E. Eichenberger ,  Bruce M. Fleischer

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30032 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/3838

摘要： Mechanisms, in a data processing system comprising a single instruction multiple data (SIMD) processor, for performing a data dependency check operation on vector element values of at least two input vector registers are provided. Two calls to a simd-check instruction are performed, one with input vector registers having a first order and one with the input vector registers having a different order. The simd-check instruction performs comparisons to determine if any data dependencies are present. Results of the two calls to the simd-check instruction are obtained and used to determine if any data dependencies are present in the at least two input vector registers. Based on the results, the SIMD processor may perform various operations.

摘要翻译： 提供了一种包括用于对至少两个输入向量寄存器的向量元素值进行数据相关性检查操作的单指令多数据（SIMD）处理器的数据处理系统中的机制。 执行对SIMD检查指令的两次调用，其中一个具有输入向量寄存器具有第一级，一个具有不同顺序的输入向量寄存器。 simd检查指令执行比较以确定是否存在任何数据依赖性。 获得对simd检查指令的两次调用的结果，并用于确定至少两个输入向量寄存器中是否存在任何数据依赖性。 基于该结果，SIMD处理器可以执行各种操作。

公开(公告)号：US20140047211A1

公开(公告)日：2014-02-13

申请号：US13572886

申请日：2012-08-13

申请人： Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair

发明人： Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair

IPC分类号： G06F15/76

CPC分类号： G06F15/8076 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/30109 ,  G06F9/34 ,  G06F9/345

摘要： An aspect includes accessing a vector register in a vector register file. The vector register file includes a plurality of vector registers and each vector register includes a plurality of elements. A read command is received at a read port of the vector register file. The read command specifies a vector register address. The vector register address is decoded by an address decoder to determine a selected vector register of the vector register file. An element address is determined for one of the plurality of elements associated with the selected vector register based on a read element counter of the selected vector register. A word is selected in a memory array of the selected vector register as read data based on the element address. The read data is output from the selected vector register based on the decoding of the vector register address by the address decoder.

摘要翻译： 一个方面包括访问向量寄存器文件中的向量寄存器。 向量寄存器文件包括多个向量寄存器，并且每个向量寄存器包括多个元素。 在向量寄存器文件的读端口处接收到读命令。 读命令指定向量寄存器地址。 向量寄存器地址由地址解码器解码，以确定向量寄存器文件的选定向量寄存器。 基于所选择的向量寄存器的读元素计数器，确定与所选向量寄存器相关联的多个元素之一的元素地址。 在所选向量寄存器的存储器阵列中选择一个字作为基于元素地址的读取数据。 基于由地址解码器对向量寄存器地址的解码，从所选向量寄存器输出读取数据。