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    Hybrid caching techniques and garbage collection using hybrid caching techniques
    1.
    发明授权
    Hybrid caching techniques and garbage collection using hybrid caching techniques 有权
    混合缓存技术和使用混合缓存技术的垃圾收集

    公开(公告)号：US08738859B2

    公开(公告)日：2014-05-27

    申请号：US13613104

    申请日：2012-09-13

    申请人： Chen-Yong Cher ,  Michael K. Gschwind

    发明人： Chen-Yong Cher ,  Michael K. Gschwind

    IPC分类号： G06F12/02 ,  G06F12/08

    CPC分类号： G06F12/0848 ,  G06F12/0253 ,  G06F12/0837 ,  G06F12/0875 ,  G06F2212/251 ,  G06F2212/253

    摘要： Hybrid caching techniques and garbage collection using hybrid caching techniques are provided. A determination of a measure of a characteristic of a data object is performed, the characteristic being indicative of an access pattern associated with the data object. A selection of one caching structure, from a plurality of caching structures, is performed in which to store the data object based on the measure of the characteristic. Each individual caching structure in the plurality of caching structures stores data objects has a similar measure of the characteristic with regard to each of the other data objects in that individual caching structure. The data object is stored in the selected caching structure and at least one processing operation is performed on the data object stored in the selected caching structure.

    摘要翻译： 提供了使用混合缓存技术的混合缓存技术和垃圾收集。 执行对数据对象的特性的度量的确定，该特性指示与数据对象相关联的访问模式。 执行从多个缓存结构中选择一个高速缓存结构，其中基于特性的测量来存储数据对象。 存储数据对象的多个高速缓存结构中的每个单独的缓存结构具有与该个别缓存结构中的每个其他数据对象相似的特征量度。 数据对象存储在所选择的缓存结构中，并且对存储在所选择的高速缓存结构中的数据对象执行至少一个处理操作。

    Thermal cycling and gradient management in three-dimensional stacked architectures
    2.
    发明授权
    Thermal cycling and gradient management in three-dimensional stacked architectures 有权
    三维堆叠架构中的热循环和梯度管理

    公开(公告)号：US08489217B2

    公开(公告)日：2013-07-16

    申请号：US12984096

    申请日：2011-01-04

    申请人： Chen-Yong Cher ,  Wilfried E. Haensch ,  Eren Kursun ,  David R. Motschman

    发明人： Chen-Yong Cher ,  Wilfried E. Haensch ,  Eren Kursun ,  David R. Motschman

    IPC分类号： G06F19/00

    CPC分类号： G06F1/3234 ,  G06F1/206

    摘要： A mechanism is provided for minimizing reliability problems in a three-dimensional (3D) integrated circuit. A set of sensors are interrogated for current data. A direction of force and a magnitude of the force are determined based on the current data for each sensor in the set of sensors for each of one or more directions between the sensor and at least one neighboring sensor thereby forming a set of forces. Each of the set of forces is used to identify one or more points of stress that are at or above the predetermined force threshold. Responsive to identifying at least one point of stress that is at or above the predetermined force threshold, one or more temperature actuation actions are initiated in order to reduce at least one point of stress in the region where the at least one point of stress is identified.

    摘要翻译： 提供了一种用于最小化三维（3D）集成电路中的可靠性问题的机制。 一组传感器被询问用于当前数据。 基于用于传感器和至少一个相邻传感器之间的一个或多个方向中的每一个的传感器组中的每个传感器的当前数据来确定力的方向和力的大小，从而形成一组力。 所述一组力中的每一个用于识别处于或高于预定力阈值的一个或多个应力点。 响应于识别处于或高于预定力阈值的至少一个应力点，启动一个或多个温度致动动作，以便在识别出至少一个应力点的区域中减少至少一个应力点 。

    Hybrid caching techniques and garbage collection using hybrid caching techniques
    3.
    发明授权
    Hybrid caching techniques and garbage collection using hybrid caching techniques 有权
    混合缓存技术和使用混合缓存技术的垃圾收集

    公开(公告)号：US08312219B2

    公开(公告)日：2012-11-13

    申请号：US12395860

    申请日：2009-03-02

    申请人： Chen-Yong Cher ,  Michael K. Gschwind

    发明人： Chen-Yong Cher ,  Michael K. Gschwind

    IPC分类号： G06F12/08 ,  G06F12/02

    CPC分类号： G06F12/0848 ,  G06F12/0253 ,  G06F12/0837 ,  G06F12/0875 ,  G06F2212/251 ,  G06F2212/253

    摘要： Hybrid caching techniques and garbage collection using hybrid caching techniques are provided. A determination of a measure of a characteristic of a data object is performed, the characteristic being indicative of an access pattern associated with the data object. A selection of one caching structure, from a plurality of caching structures, is performed in which to store the data object based on the measure of the characteristic. Each individual caching structure in the plurality of caching structures stores data objects has a similar measure of the characteristic with regard to each of the other data objects in that individual caching structure. The data object is stored in the selected caching structure and at least one processing operation is performed on the data object stored in the selected caching structure.

    摘要翻译： 提供了使用混合缓存技术的混合缓存技术和垃圾收集。 执行对数据对象的特性的度量的确定，该特性指示与数据对象相关联的访问模式。 执行从多个缓存结构中选择一个高速缓存结构，其中基于特性的测量来存储数据对象。 存储数据对象的多个高速缓存结构中的每个单独的缓存结构具有与该个别缓存结构中的每个其他数据对象相似的特征量度。 数据对象存储在所选择的缓存结构中，并且对存储在所选择的高速缓存结构中的数据对象执行至少一个处理操作。

    METHOD AND SYSTEM FOR CONTROLLING POWER IN A CHIP THROUGH A POWER-PERFORMANCE MONITOR AND CONTROL UNIT
    4.
    发明申请
    METHOD AND SYSTEM FOR CONTROLLING POWER IN A CHIP THROUGH A POWER-PERFORMANCE MONITOR AND CONTROL UNIT 有权
    通过功率性能监视器和控制单元控制芯片中的功率的方法和系统

    公开(公告)号：US20120054528A1

    公开(公告)日：2012-03-01

    申请号：US13292712

    申请日：2011-11-09

    申请人： PRADIP BOSE ,  Alper Buyuktosunoglu ,  Chen-Yong Cher ,  Prabhakar N. Kudva

    发明人： PRADIP BOSE ,  Alper Buyuktosunoglu ,  Chen-Yong Cher ,  Prabhakar N. Kudva

    IPC分类号： G06F1/00 ,  G06F11/30

    CPC分类号： G06F1/206 ,  G06F1/3203 ,  Y02D10/16

    摘要： A system and method for controlling power and performance in a microprocessor system includes a monitoring and control system integrated into a microprocessor system. The monitoring and control system includes a hierarchical architecture having a plurality of layers. Each layer in the hierarchal architecture is responsive to commands from a higher level, and the commands provide instructions on operations and power distribution, such that the higher levels provide modes of operation and budgets to lower levels and the lower levels provide feedback to the higher levels to control and manage power usage in the microprocessor system both globally and locally.

    摘要翻译： 用于控制微处理器系统中的功率和性能的系统和方法包括集成到微处理器系统中的监视和控制系统。 监视和控制系统包括具有多个层的层次结构。 层次结构中的每层都响应来自更高级别的命令，并且命令提供关于操作和功率分配的指令，使得较高级别提供操作模式和预算以降低级别，并且较低级别向较高级别提供反馈 在全球和本地控制和管理微处理器系统中的电力使用。

    Power Management for Systems On a Chip
    5.
    发明申请
    Power Management for Systems On a Chip 有权
    电源管理系统芯片

    公开(公告)号：US20110191603A1

    公开(公告)日：2011-08-04

    申请号：US12700513

    申请日：2010-02-04

    申请人： Chen-Yong Cher ,  Tejas S. Karkhanis ,  Srinivasan Ramani

    发明人： Chen-Yong Cher ,  Tejas S. Karkhanis ,  Srinivasan Ramani

    IPC分类号： G06F1/00

    CPC分类号： G06F1/00 ,  Y02D10/124

    摘要： A system for controlling a multitasking microprocessor system includes an interconnect, a plurality of processing units connected to the interconnect forming a single-source, single-sink flow network, wherein the plurality of processing units pass data between one another from the single-source to the single-sink, and a monitor connected to the interconnect for monitoring a portion of a resource consumed by each of the plurality of processing units and for controlling the plurality of processing units according to a predetermined budget for the resource to control a data overflow condition, wherein the monitor controls performance and power modes of the plurality of processing units.

    摘要翻译： 用于控制多任务微处理器系统的系统包括互连，连接到形成单源单一信宿流网络的互连的多个处理单元，其中所述多个处理单元将数据从单一源传递到 所述单个接收器和连接到所述互连的监视器，用于监视所述多个处理单元中的每一个所消耗的资源的一部分，并且用于根据所述资源的预定预算控制所述多个处理单元以控制数据溢出条件 ，其中所述监视器控制所述多个处理单元的性能和功率模式。

    EFFICIENCY OF STATIC CORE TURN-OFF IN A SYSTEM-ON-A-CHIP WITH VARIATION
    6.
    发明申请
    EFFICIENCY OF STATIC CORE TURN-OFF IN A SYSTEM-ON-A-CHIP WITH VARIATION 失效
    静态芯片在带有变化的系统中的关闭效率

    公开(公告)号：US20110172984A1

    公开(公告)日：2011-07-14

    申请号：US12727984

    申请日：2010-03-19

    申请人： Chen-Yong Cher ,  Paul W. Coteus ,  Alan Gara ,  Eren Kursun ,  David P. Paulsen ,  Brian A. Schuelke ,  John E. Sheets, II ,  Shurong Tian

    发明人： Chen-Yong Cher ,  Paul W. Coteus ,  Alan Gara ,  Eren Kursun ,  David P. Paulsen ,  Brian A. Schuelke ,  John E. Sheets, II ,  Shurong Tian

    IPC分类号： G06F9/455

    CPC分类号： G06F1/3203 ,  G06F1/206 ,  G06F1/3237 ,  G06F11/24 ,  Y02D10/128 ,  Y02D10/16

    摘要： A processor-implemented method for improving efficiency of a static core turn-off in a multi-core processor with variation, the method comprising: conducting via a simulation a turn-off analysis of the multi-core processor at the multi-core processor's design stage, wherein the turn-off analysis of the multi-core processor at the multi-core processor's design stage includes a first output corresponding to a first multi-core processor core to turn off; conducting a turn-off analysis of the multi-core processor at the multi-core processor's testing stage, wherein the turn-off analysis of the multi-core processor at the multi-core processor's testing stage includes a second output corresponding to a second multi-core processor core to turn off; comparing the first output and the second output to determine if the first output is referring to the same core to turn off as the second output; outputting a third output corresponding to the first multi-core processor core if the first output and the second output are both referring to the same core to turn off.

    摘要翻译： 一种用于提高多核处理器中的静态核心关断的效率的处理器实现的方法，所述方法包括：通过模拟在多核处理器的设计处进行多核处理器的关断分析 其中所述多核处理器的设计阶段的所述多核处理器的关断分析包括对应于第一多核处理器核的第一输出关闭; 在多核处理器的测试阶段对多核处理器进行关断分析，其中多核处理器的测试阶段的多核处理器的关断分析包括对应于第二多核处理器的第二多输出 核心处理器核心关闭; 比较第一输出和第二输出以确定第一输出是否指相同的磁芯作为第二输出关闭; 如果第一输出和第二输出均指向相同的核来关闭，则输出对应于第一多核处理器核心的第三输出。

    Hybrid Caching Techniques and Garbage Collection Using Hybrid Caching Techniques
    7.
    发明申请
    Hybrid Caching Techniques and Garbage Collection Using Hybrid Caching Techniques 有权
    混合缓存技术和使用混合缓存技术的垃圾收集

    公开(公告)号：US20100223429A1

    公开(公告)日：2010-09-02

    申请号：US12395860

    申请日：2009-03-02

    申请人： Chen-Yong Cher ,  Michael K. Gschwind

    发明人： Chen-Yong Cher ,  Michael K. Gschwind

    IPC分类号： G06F12/08 ,  G06F12/00

    CPC分类号： G06F12/0848 ,  G06F12/0253 ,  G06F12/0837 ,  G06F12/0875 ,  G06F2212/251 ,  G06F2212/253

    摘要： Hybrid caching techniques and garbage collection using hybrid caching techniques are provided. A determination of a measure of a characteristic of a data object is performed, the characteristic being indicative of an access pattern associated with the data object. A selection of one caching structure, from a plurality of caching structures, is performed in which to store the data object based on the measure of the characteristic. Each individual caching structure in the plurality of caching structures stores data objects has a similar measure of the characteristic with regard to each of the other data objects in that individual caching structure. The data object is stored in the selected caching structure and at least one processing operation is performed on the data object stored in the selected caching structure.

    摘要翻译： 提供了使用混合缓存技术的混合缓存技术和垃圾收集。 执行对数据对象的特性的度量的确定，该特性指示与数据对象相关联的访问模式。 执行从多个缓存结构中选择一个高速缓存结构，其中基于特性的测量来存储数据对象。 存储数据对象的多个高速缓存结构中的每个单独的缓存结构具有与该个别缓存结构中的每个其他数据对象相似的特征量度。 数据对象存储在所选择的缓存结构中，并且对存储在所选择的高速缓存结构中的数据对象执行至少一个处理操作。

    METHOD AND SYSTEM OF PEAK POWER ENFORCEMENT VIA AUTONOMOUS TOKEN-BASED CONTROL AND MANAGEMENT
    8.
    发明申请
    METHOD AND SYSTEM OF PEAK POWER ENFORCEMENT VIA AUTONOMOUS TOKEN-BASED CONTROL AND MANAGEMENT 有权
    通过自动基于方法的控制和管理，峰值功率执行的方法和系统

    公开(公告)号：US20090089602A1

    公开(公告)日：2009-04-02

    申请号：US11862559

    申请日：2007-09-27

    申请人： Pradip Bose ,  Alper Buyuktosunoglu ,  Chen-Yong Cher ,  Zhigang Hu ,  Hans Jacobson ,  Prabhakar N. Kudva ,  Vijayalakshmi Srinivasan ,  Victor Zyuban

    发明人： Pradip Bose ,  Alper Buyuktosunoglu ,  Chen-Yong Cher ,  Zhigang Hu ,  Hans Jacobson ,  Prabhakar N. Kudva ,  Vijayalakshmi Srinivasan ,  Victor Zyuban

    IPC分类号： G06F1/28

    CPC分类号： G06F1/3287 ,  G06F1/206 ,  G06F9/3836 ,  G06F9/3869 ,  G06F9/5094 ,  Y02D10/16 ,  Y02D10/171 ,  Y02D10/22 ,  Y02D50/20

    摘要： A method of power management of a system of connected components includes initializing a token allocation map across the connected components, wherein each component is assigned a power budget as determined by a number of allocated tokens in the token allocation map, monitoring utilization sensor inputs and command state vector inputs, determining, at first periodic time intervals, a current performance level, a current power consumption level and an assigned power budget for the system based on the utilization sensor inputs and the command state vector inputs, and determining, at second periodic time intervals, a token re-allocation map based on the current performance level, the current power consumption level and the assigned power budget for the system, according to a re-assigned power budget of at least one of the connected components, while enforcing a power consumption limit based on a total number of allocated tokens in the system.

    摘要翻译： 一种连接组件的系统的电源管理方法包括：在所连接的组件之间初始化令牌分配映射，其中每个组件被分配由令牌分配映射中的分配的令牌数量确定的功率预算，监视利用率传感器输入和命令 状态向量输入，基于所述利用传感器输入和所述命令状态向量输入，以第一周期性时间间隔确定所述系统的当前性能水平，当前功耗级别和所分配的功率预算，以及在所述第二周期时间 间隔，基于当前性能水平的令牌重新分配图，当前功耗水平和系统的分配的功率预算，根据至少一个连接的组件的重新分配的功率预算，同时执行功率 基于系统中分配的令牌总数的消耗限制。

    METHOD AND SYSTEM FOR CONTROLLING POWER IN A CHIP THROUGH A POWER-PERFORMANCE MONITOR AND CONTROL UNIT
    9.
    发明申请
    METHOD AND SYSTEM FOR CONTROLLING POWER IN A CHIP THROUGH A POWER-PERFORMANCE MONITOR AND CONTROL UNIT 失效
    通过功率性能监视器和控制单元控制芯片中的功率的方法和系统

    公开(公告)号：US20090049318A1

    公开(公告)日：2009-02-19

    申请号：US12132044

    申请日：2008-06-03

    申请人： Pradip Bose ,  Alper Buyuktosunoglu ,  Chen-Yong Cher ,  Prabhakar N. Kudva

    发明人： Pradip Bose ,  Alper Buyuktosunoglu ,  Chen-Yong Cher ,  Prabhakar N. Kudva

    IPC分类号： G06F1/32

    CPC分类号： G06F1/206 ,  G06F1/3203 ,  Y02D10/16

    摘要： A system and method for controlling power and performance in a microprocessor system includes a monitoring and control system integrated into a microprocessor system. The monitoring and control system includes a hierarchical architecture having a plurality of layers. Each layer in the hierarchal architecture is responsive to commands from a higher level, and the commands provide instructions on operations and power distribution, such that the higher levels provide modes of operation and budgets to lower levels and the lower levels provide feedback to the higher levels to control and manage power usage in the microprocessor system both globally and locally.

    摘要翻译： 用于控制微处理器系统中的功率和性能的系统和方法包括集成到微处理器系统中的监视和控制系统。 监视和控制系统包括具有多个层的层次结构。 层次结构中的每层都响应来自更高级别的命令，并且命令提供关于操作和功率分配的指令，使得较高级别提供操作模式和预算以降低级别，并且较低级别向较高级别提供反馈 在全球和本地控制和管理微处理器系统中的电力使用。