公开(公告)号：US09652243B2

公开(公告)日：2017-05-16

申请号：US13172218

申请日：2011-06-29

申请人： Ioana Monica Burcea ,  Alper Buyuktosunoglu ,  Brian Robert Prasky ,  Vijayalakshmi Srinivasan

发明人： Ioana Monica Burcea ,  Alper Buyuktosunoglu ,  Brian Robert Prasky ,  Vijayalakshmi Srinivasan

IPC分类号： G06F9/38

CPC分类号： G06F9/3836 ,  G06F9/3851

摘要： Systems and methods for predicting out-of-order instruction-level parallelism (ILP) of threads being executed in a multi-threaded processor and prioritizing scheduling thereof are described herein. One aspect provides for tracking completion of instructions using a global completion table having a head segment and a tail segment; storing prediction values for each instruction in a prediction table indexed via instruction identifiers associated with each instruction, a prediction value being configured to indicate an instruction is predicted to issue from one of: the head segment and the tail segment; and predicting threads with more instructions issuing from the tail segment have a higher degree of out-of-order instruction-level parallelism. Other embodiments and aspects are also described herein.

公开(公告)号：US08826095B2

公开(公告)日：2014-09-02

申请号：US13041248

申请日：2011-03-04

申请人： Philip George Emma ,  Wing K. Luk ,  Thomas R. Puzak ,  Vijayalakshmi Srinivasan

发明人： Philip George Emma ,  Wing K. Luk ,  Thomas R. Puzak ,  Vijayalakshmi Srinivasan

IPC分类号： H03M13/00

CPC分类号： G06F12/0802 ,  G06F11/1064 ,  G06F11/1666

摘要： A hardened store-in cache system includes a store-in cache having lines of a first linesize stored with checkbits, wherein the checkbits include byte-parity bits, and an ancillary store-only cache (ASOC) that holds a copy of most recently stored-to lines of the store-in cache. The ASOC includes fewer lines than the store-in cache, each line of the ASOC having the first linesize stored with the checkbits.

摘要翻译： 硬化的存储缓存系统包括具有存储有校验位的第一行的行的存储高速缓存，其中校验位包括字节奇偶校验位，以及保存最近存储的副本的辅助存储高速缓存（ASOC） 到存储缓存中的行。 ASOC包括比存储缓存更少的行，ASOC的每一行都具有与检查位一起存储的第一行。

公开(公告)号：US08024513B2

公开(公告)日：2011-09-20

申请号：US11949904

申请日：2007-12-04

申请人： John E. Barth, Jr. ,  Philip G. Emma ,  Erik L. Hedberg ,  Hillery C. Hunter ,  Peter A. Sandon ,  Vijayalakshmi Srinivasan ,  Arnold S. Tran

发明人： John E. Barth, Jr. ,  Philip G. Emma ,  Erik L. Hedberg ,  Hillery C. Hunter ,  Peter A. Sandon ,  Vijayalakshmi Srinivasan ,  Arnold S. Tran

IPC分类号： G06F12/00

CPC分类号： G06F12/0893 ,  Y02D10/13

摘要： A method for implementing dynamic refresh protocols for DRAM based cache includes partitioning a DRAM cache into a refreshable portion and a non-refreshable portion, and assigning incoming individual cache lines to one of the refreshable portion and the non-refreshable portion of the cache based on a usage history of the cache lines. Cache lines corresponding to data having a usage history below a defined frequency are assigned to the refreshable portion of the cache, and cache lines corresponding to data having a usage history at or above the defined frequency are assigned to the non-refreshable portion of the cache.

摘要翻译： 一种用于实现基于DRAM的高速缓存的动态刷新协议的方法包括将DRAM高速缓存划分为可刷新部分和不可刷新部分，以及基于以下方式将输入的各个高速缓存行分配到高速缓存的可刷新部分和不可刷新部分之一： 高速缓存行的使用历史。 对应于具有低于定义频率的使用历史的数据的缓存线被分配给高速缓存的可刷新部分，并且与具有等于或高于定义频率的使用历史的数据相对应的高速缓存行被分配给高速缓存的不可刷新部分 。

公开(公告)号：US20110055515A1

公开(公告)日：2011-03-03

申请号：US12552676

申请日：2009-09-02

申请人： Khubaib Khubaib ,  Moinuddin Khalil Ahmed Qureshi ,  Vijayalakshmi Srinivasan

发明人： Khubaib Khubaib ,  Moinuddin Khalil Ahmed Qureshi ,  Vijayalakshmi Srinivasan

IPC分类号： G06F12/06

CPC分类号： G06F12/0833 ,  G06F12/0831 ,  G06F12/1027 ,  Y02D10/13

摘要： Disclosed is an apparatus to reduce broadcasts in multiprocessors including a plurality of processors; a plurality of memory caches associated with the processors; a plurality of translation lookaside buffers (TLBs) associated with the processors; and a physical memory shared with the processors memory caches and TLBs; wherein each TLB includes a plurality of entries for translation of a page of addresses from virtual memory to physical memory, each TLB entry having page characterization information indicating whether the page is private to one processor or shared with more than one processor. Also disclosed is a computer program product and method to reduce broadcasts in multiprocessors.

摘要翻译： 公开了一种减少包括多个处理器在内的多处理器中的广播的装置; 与所述处理器相关联的多个存储器高速缓存; 与处理器相关联的多个翻译后备缓冲器（TLB）; 以及与处理器存储器高速缓存和TLB共享的物理存储器; 其中每个TLB包括用于将地址页从虚拟存储器翻译成物理存储器的多个条目，每个TLB条目具有指示该页面是一个处理器是专用还是与一个以上处理器共享的页面表征信息。 还公开了一种用于减少多处理器中的广播的计算机程序产品和方法。

公开(公告)号：US20110026318A1

公开(公告)日：2011-02-03

申请号：US12533548

申请日：2009-07-31

申请人： Michele M. Franceschini ,  Luis A. Lastras-Montano ,  Moinuddin K. Qureshi ,  Vijayalakshmi Srinivasan

发明人： Michele M. Franceschini ,  Luis A. Lastras-Montano ,  Moinuddin K. Qureshi ,  Vijayalakshmi Srinivasan

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G06F13/1642 ,  G06F13/161

摘要： Iterative write pausing techniques to improve read latency of memory systems including memory systems with phase change memory (PCM) devices. A PCM device includes a plurality of memory locations and a mechanism for executing an iterative write to one or more of the memory locations in response to receiving a write command that includes data to be written. The executing includes initiating the iterative write, updating a state of the iterative write, pausing the iterative write including saving the state in response to receiving a pause command, and resuming the iterative write in response to receiving a resume command. The resuming is responsive to the saved state and to the data to be written.

摘要翻译： 迭代写暂停技术，以提高内存系统（包括具有相变存储器（PCM）设备的存储器系统）的读取延迟。 PCM设备包括多个存储器位置和用于响应于接收到包括要写入的数据的写入命令而执行对一个或多个存储器位置的迭代写入的机制。 执行包括启动迭代写入，更新迭代写入的状态，暂停迭代写入，包括响应于接收到暂停命令而保存状态，以及响应于接收到恢复命令恢复迭代写入。 恢复响应于保存的状态和要写入的数据。

公开(公告)号：US20090144506A1

公开(公告)日：2009-06-04

申请号：US11949904

申请日：2007-12-04

申请人： John E. Barth, JR. ,  Philip G. Emma ,  Erik L. Hedberg ,  Hillery C. Hunter ,  Peter A. Sandon ,  Vijayalakshmi Srinivasan ,  Arnold S. Tran

发明人： John E. Barth, JR. ,  Philip G. Emma ,  Erik L. Hedberg ,  Hillery C. Hunter ,  Peter A. Sandon ,  Vijayalakshmi Srinivasan ,  Arnold S. Tran

IPC分类号： G06F12/08

CPC分类号： G06F12/0893 ,  Y02D10/13

摘要： A method for implementing dynamic refresh protocols for DRAM based cache includes partitioning a DRAM cache into a refreshable portion and a non-refreshable portion, and assigning incoming individual cache lines to one of the refreshable portion and the non-refreshable portion of the cache based on a usage history of the cache lines. Cache lines corresponding to data having a usage history below a defined frequency are assigned to the refreshable portion of the cache, and cache lines corresponding to data having a usage history at or above the defined frequency are assigned to the non-refreshable portion of the cache.

摘要翻译： 一种用于实现基于DRAM的高速缓存的动态刷新协议的方法包括将DRAM高速缓存划分为可刷新部分和不可刷新部分，以及基于以下方式将输入的各个高速缓存行分配到高速缓存的可刷新部分和不可刷新部分之一： 高速缓存行的使用历史。 对应于具有低于定义频率的使用历史的数据的高速缓存行被分配给高速缓存的可刷新部分，并且与具有等于或高于定义频率的使用历史的数据相对应的高速缓存行被分配给高速缓存的不可刷新部分 。

公开(公告)号：US07493480B2

公开(公告)日：2009-02-17

申请号：US10197714

申请日：2002-07-18

申请人： Philip G. Emma ,  Klaus J. Getzlaff ,  Allan M. Hartstein ,  Thomas Pflueger ,  Thomas R. Puzak ,  Eric Mark Schwarz ,  Vijayalakshmi Srinivasan

发明人： Philip G. Emma ,  Klaus J. Getzlaff ,  Allan M. Hartstein ,  Thomas Pflueger ,  Thomas R. Puzak ,  Eric Mark Schwarz ,  Vijayalakshmi Srinivasan

IPC分类号： G06F9/00

CPC分类号： G06F9/3806

摘要： A two level branch history table (TLBHT) is substantially improved by providing a mechanism to prefetch entries from the very large second level branch history table (L2 BHT) into the active (very fast) first level branch history table (L1 BHT) before the processor uses them in the branch prediction process and at the same time prefetch cache misses into the instruction cache. The mechanism prefetches entries from the very large L2 BHT into the very fast L1 BHT before the processor uses them in the branch prediction process. A TLBHT is successful because it can prefetch branch entries into the L1 BHT sufficiently ahead of the time the entry is needed. This feature of the TLBHT is also used to prefetch instructions into the cache ahead of their use. In fact, the timeliness of the prefetches produced by the TLBHT can be used to remove most of the cycle time penalty incurred by cache misses.

摘要翻译： 通过提供一种将超大型第二级分支历史表（L2 BHT）中的条目预取到活动（非常快）的第一级分支历史表（L1 BHT）中的条目之前，两级分支历史表（TLBHT）被大大改善 处理器在分支预测过程中使用它们，并且同时将高速缓存未命中预取到指令高速缓存中。 在处理器在分支预测过程中使用它们之前，该机制将从非常大的L2 BHT中将条目预取到非常快的L1 BHT中。 TLBHT是成功的，因为它可以在需要输入的时间之前将分支条目预取到L1 BHT中。 TLBHT的这个功能也用于在使用之前将指令预取到高速缓存中。 实际上，由TLBHT产生的预取的及时性可以用来消除高速缓存未命中引起的大部分周期时间损失。

公开(公告)号：US07454573B2

公开(公告)日：2008-11-18

申请号：US11035350

申请日：2005-01-13

申请人： Alper Buyuktosunoglu ,  Zhigang Hu ,  Jude A. Rivers ,  John T. Robinson ,  Xiaowei Shen ,  Vijayalakshmi Srinivasan

发明人： Alper Buyuktosunoglu ,  Zhigang Hu ,  Jude A. Rivers ,  John T. Robinson ,  Xiaowei Shen ,  Vijayalakshmi Srinivasan

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F12/0897 ,  G06F12/128 ,  Y02D10/13

摘要： A hardware based method for determining when to migrate cache lines to the cache bank closest to the requesting processor to avoid remote access penalty for future requests. In a preferred embodiment, decay counters are enhanced and used in determining the cost of retaining a line as opposed to replacing it while not losing the data. In one embodiment, a minimization of off-chip communication is sought; this may be particularly useful in a CMP environment.

摘要翻译： 一种基于硬件的方法，用于确定何时将高速缓存行迁移到最靠近请求处理器的缓存库，以避免对未来请求的远程访问损失。 在优选实施例中，衰减计数器被增强并用于确定保留线的成本，而不是在不丢失数据的情况下替换它。 在一个实施例中，寻求片外通信的最小化; 这可能在CMP环境中特别有用。

公开(公告)号：US20080222358A1

公开(公告)日：2008-09-11

申请号：US11683285

申请日：2007-03-07

申请人： Philip George Emma ,  Wing K. Luk ,  Thomas R. Puzak ,  Vijayalakshmi Srinivasan

发明人： Philip George Emma ,  Wing K. Luk ,  Thomas R. Puzak ,  Vijayalakshmi Srinivasan

IPC分类号： G06F12/08

CPC分类号： G06F12/0802 ,  G06F11/1064 ,  G06F11/1666

摘要： A system and method of providing a cache system having a store-in policy and affording the advantages of store-in cache operation, while simultaneously providing protection against soft-errors in locally modified data, which would normally preclude the use of a store-in cache when reliability is paramount. The improved store-in cache mechanism includes a store-in L1 cache, at least one higher-level storage hierarchy; an ancillary store-only cache (ASOC) that holds most recently stored-to lines of the store-in L1 cache, and a cache controller that controls storing of data to the ancillary store-only cache (ASOC) and recovering of data from the ancillary store-only cache (ASOC) such that the data from the ancillary store-only cache (ASOC) is used only if parity errors are encountered in the store-in L1 cache.

摘要翻译： 提供具有存储策略并提供存储高速缓存操作的优点的缓存系统的系统和方法，同时提供对本地修改的数据中的软错误的保护，这通常会阻止使用存储 缓存当可靠性至关重要时。 改进的存储高速缓存机制包括存储L1高速缓存，至少一个更高级别的存储层级; 保存最近存储在L1高速缓存中的行的辅助存储专用缓存（ASOC）以及控制将数据存储到辅助存储高速缓存（ASOC）并从 辅助存储高速缓存（ASOC），使得只有在存储的L1高速缓存中遇到奇偶校验错误时才使用来自辅助存储高速缓存（ASOC）的数据。

公开(公告)号：US07134028B2

公开(公告)日：2006-11-07

申请号：US10428170

申请日：2003-05-01

申请人： Pradip Bose ,  David M. Brooks ,  Peter W. Cook ,  Philip G. Emma ,  Michael K. Gschwind ,  Stanley E. Schuster ,  Vijayalakshmi Srinivasan

发明人： Pradip Bose ,  David M. Brooks ,  Peter W. Cook ,  Philip G. Emma ,  Michael K. Gschwind ,  Stanley E. Schuster ,  Vijayalakshmi Srinivasan

IPC分类号： G06F1/26 ,  G06F1/32

CPC分类号： G06F9/3869 ,  G06F1/3203 ,  G06F1/3243 ,  G06F1/3246 ,  G06F1/3287 ,  Y02D10/152 ,  Y02D10/171

摘要： An integrated circuit (IC) including unit power control, leakage reduction circuit for controllably reducing leakage power with reduced LdI/dt noise in the IC and, an activity prediction unit invoking active/dormant states in IC units. The prediction unit determines turn on and turn off times for each IC unit. The prediction unit controls a supply voltage select circuit selectively passing a supply voltage to a separate supply line at the predicted turn on time and selectively blocking the supply voltage at the predicted turn off time.

摘要翻译： 包括单元功率控制的集成电路（IC），用于可控地减少IC中的LdI / dt噪声的泄漏功率的泄漏降低电路，以及在IC单元中调用主动/休眠状态的活动预测单元。 预测单元确定每个IC单元的导通和关闭时间。 预测单元控制电源电压选择电路，其在预测的导通时间选择性地将电源电压传递到单独的电源线，并且在预测的关断时间选择性地阻断电源电压。