公开(公告)号：US08471624B2

公开(公告)日：2013-06-25

申请号：US13037343

申请日：2011-02-28

申请人： Stefan Bonsels ,  Cedric Lichtenau ,  Antje Mueller ,  Thomas Pflueger ,  Friedrich Schroeder

发明人： Stefan Bonsels ,  Cedric Lichtenau ,  Antje Mueller ,  Thomas Pflueger ,  Friedrich Schroeder

IPC分类号： G05F3/02

CPC分类号： G05F1/56

摘要： The present invention relates to a method for controlling the supply voltage for an integrated circuit, which is connected to a voltage regulation module via a sense line, a voltage supply line and a bus wherein the supply voltage is provided by the voltage regulation module (10) via the voltage supply line. The supply voltage is composed of a reference voltage and a number of additional voltage levels. The reference voltage is defined by a voltage source and controlled by the integrated circuit via the bus, and the number of additional voltage levels is determined by the integrated circuit and send to the voltage regulation module via the sense line. Further the present invention relates to a corresponding apparatus with a voltage regulation module and an integrated circuit.

摘要翻译： 本发明涉及一种用于控制集成电路的电源电压的方法，该集成电路通过感测线，电压供应线和总线连接到电压调节模块，其中电源电压由电压调节模块（10 ）通过电源线。 电源电压由参考电压和多个附加电压电平组成。 参考电压由电压源定义，并通过总线由集成电路控制，附加电压电平的数量由集成电路确定，并通过感测线发送到电压调节模块。 此外，本发明涉及具有电压调节模块和集成电路的相应装置。

公开(公告)号：US08365006B2

公开(公告)日：2013-01-29

申请号：US12836103

申请日：2010-07-14

申请人： Steven M. Douskey ,  Thomas Pflueger ,  Edward M. Seymour ,  Timothy M. Skergan

发明人： Steven M. Douskey ,  Thomas Pflueger ,  Edward M. Seymour ,  Timothy M. Skergan

IPC分类号： G06F1/10

CPC分类号： G06F1/04 ,  G06F21/70

摘要： For disabling a first function in an information handling system, a dynamic signal is disabled. The first function is inoperable in response to the dynamic signal being disabled. At least a second function in the information handling system is operable irrespective of whether the dynamic signal is disabled.

摘要翻译： 为了禁用信息处理系统中的第一个功能，禁用动态信号。 响应于动态信号被禁用，第一个功能是无法操作的。 无论动态信号是否被禁用，信息处理系统中的至少第二功能是可操作的。

公开(公告)号：US07865749B2

公开(公告)日：2011-01-04

申请号：US10595520

申请日：2003-10-31

申请人： Peter A. Sandon ,  Cedric Lichtenau ,  Martin Recktenwald ,  Thomas Pflueger ,  Rolf Hilgendorf

发明人： Peter A. Sandon ,  Cedric Lichtenau ,  Martin Recktenwald ,  Thomas Pflueger ,  Rolf Hilgendorf

IPC分类号： G06F1/32

CPC分类号： H03L7/16 ,  G06F1/08

摘要： A method and apparatus for changing a clock frequency in a system (10) comprising a plurality of synchronous integrated circuit chips (12, 14, 16), and a circuit (20) for implementing the frequency change. The method includes: detecting a change in processing requirements in one of the plurality of synchronous integrated circuit chips; notifying the plurality of synchronous integrated circuit chips that a clock frequency change is to occur; achieving a quiescent bus state in each of the plurality of synchronous integrated circuit chips; notifying the plurality of synchronous integrated circuit chips that the clock frequency change can occur; and changing the clock frequency of the plurality of integrated circuit chips.

摘要翻译： 一种用于改变包括多个同步集成电路芯片（12,14,16）的系统（10）中的时钟频率的方法和装置，以及用于实现频率变化的电路（20）。 该方法包括：检测多个同步集成电路芯片之一中处理要求的变化; 通知多个同步集成电路芯片发生时钟频率变化; 在所述多个同步集成电路芯片的每一个中实现静态总线状态; 通知多个同步集成电路芯片可能发生时钟频率变化; 以及改变多个集成电路芯片的时钟频率。

公开(公告)号：US20100332798A1

公开(公告)日：2010-12-30

申请号：US12825402

申请日：2010-06-29

申请人： Martin Doerr ,  Hubert Eichner ,  Markus Kaltenbach ,  Volker Koch ,  Ulrich Mayer ,  Thomas Pflueger ,  Thomas Schlipf ,  Cordt Starke ,  Jan Van Lunteren

发明人： Martin Doerr ,  Hubert Eichner ,  Markus Kaltenbach ,  Volker Koch ,  Ulrich Mayer ,  Thomas Pflueger ,  Thomas Schlipf ,  Cordt Starke ,  Jan Van Lunteren

IPC分类号： G06F15/76 ,  G06F9/02

CPC分类号： G06F9/3012 ,  G06F9/3828 ,  G06F9/3891

摘要： A processor subunit for a processor for processing data. The processor subunit includes registers, and at least one functional unit for executing instructions on data. One or more registers of the registers are connected to an input of the at least one functional unit, where each register connected to the input of the at least one functional unit which has an input multiplexer. One or more registers of the registers are connected to an output of the at least one functional unit, where each register connected to the output of the at least one functional unit which has an input multiplexer. At least one output bus is connected to at least one register. At least one input bus is connected to at least one register. The processor subunit may be used in a processor, which may be used in a data streaming accelerator.

摘要翻译： 用于处理数据的处理器的处理器子单元。 处理器子单元包括寄存器和用于执行数据指令的至少一个功能单元。 寄存器的一个或多个寄存器被连接到至少一个功能单元的输入，其中每个寄存器连接到具有输入多路复用器的至少一个功能单元的输入。 寄存器的一个或多个寄存器被连接到至少一个功能单元的输出，其中每个寄存器连接到具有输入多路复用器的至少一个功能单元的输出端。 至少一个输出总线连接到至少一个寄存器。 至少一个输入总线连接到至少一个寄存器。 处理器子单元可以用在可以在数据流加速器中使用的处理器中。

公开(公告)号：US20100161867A1

公开(公告)日：2010-06-24

申请号：US12343594

申请日：2008-12-24

申请人： Matthias Fertig ,  Tilman Gloekler ,  Ralph C. Koester ,  Alexander Erik Mericas ,  Thomas Pflueger

发明人： Matthias Fertig ,  Tilman Gloekler ,  Ralph C. Koester ,  Alexander Erik Mericas ,  Thomas Pflueger

IPC分类号： G06F13/36

CPC分类号： G06F13/4247 ,  G06F11/3466 ,  G06F11/348 ,  G06F11/349 ,  G06F2201/88

摘要： A system and associated method for distributing signals with efficiency over a microprocessor. A performance monitoring unit (PMU) sends configuration signals to a unit to monitor an event occurring on the unit. The unit is attached to a configuration bus and an event bus that are daisy-chained from PMU to other units in the microprocessor. The configuration bus transmits configuration signals from the PMU to the unit to set the unit to report the event. The unit sends event signals to the PMU through the event bus. The unit is configured upon receiving configuration signals comprising a base address of a bus ramp of the unit. A number of units and a number of events for monitoring is flexibly selected by adjusting a length of bit fields within configuration signals.

摘要翻译： 一种用于通过微处理器分配信号的系统和相关方法。 性能监控单元（PMU）将配置信号发送到单元以监视本机发生的事件。 该单元连接到配置总线和从PMU菊花链到微处理器中的其他单元的事件总线。 配置总线将配置信号从PMU发送到单元以设置单元以报告事件。 该单元通过事件总线向PMU发送事件信号。 该单元被配置为接收到包括该单元的总线斜坡的基地址的配置信号。 通过调整配置信号中的位域的长度，可灵活选择多个单元和多个监控事件。

公开(公告)号：US07602874B2

公开(公告)日：2009-10-13

申请号：US11340449

申请日：2006-01-26

申请人： Rolf Hilgendorf ,  Jens Kuenzer ,  Cedric Lichtenau ,  Thomas Pflueger ,  Martin Recktenwald ,  Andreas Schmid

发明人： Rolf Hilgendorf ,  Jens Kuenzer ,  Cedric Lichtenau ,  Thomas Pflueger ,  Martin Recktenwald ,  Andreas Schmid

IPC分类号： H04L7/00

CPC分类号： G06F1/14 ,  G04F10/04 ,  H03L7/06

摘要： A mechanism provides accurate time-based counters for scaling operating frequencies of microprocessors. The mechanism makes use of a time-based counter circuit configuration in which a fixed frequency clock is derived from a PLL of the clock generation circuit of the microprocessor and is used to feed the external and internal timebase logic as well as a timebase accumulator counter. The timebase accumulator counter accumulates the tick events from the timebase logic between two core clocks. The accumulated value is transferred to the core clock domain on every clock edge of a scalable clock and the accumulator is then reset. Because the accumulated ticks are transferred to the core clock domain before the accumulator is reset, no ticks are ever lost using the circuitry of the illustrative embodiment.

摘要翻译： 一种机制提供了精确的基于时间的计数器来缩放微处理器的工作频率。 该机制利用基于时间的计数器电路配置，其中从微处理器的时钟产生电路的PLL导出固定频率时钟，并且用于馈送外部和内部时基逻辑以及时基累加器计数器。 时基累加器计数器从两个核心时钟之间的时基逻辑累加tick事件。 累加值在可伸缩时钟的每个时钟沿传输到核心时钟域，然后累加器复位。 因为在累加器复位之前累积的刻度被传送到核心时钟域，所以使用说明性实施例的电路不会丢失任何刻度。

公开(公告)号：US20090140362A1

公开(公告)日：2009-06-04

申请号：US12325195

申请日：2008-11-29

申请人： Matthias Fertig ,  Nikolaj Moll ,  Thomas E. Morf ,  Thomas Pflueger ,  Jonas R. Weiss

发明人： Matthias Fertig ,  Nikolaj Moll ,  Thomas E. Morf ,  Thomas Pflueger ,  Jonas R. Weiss

IPC分类号： H01L31/00

CPC分类号： H01L27/1446 ,  H01L31/02327

摘要： A photo detector comprising a grating (PC). The grating (PC) is arranged on top of a surface of an active semiconductor layer. The grating (PC) is patterned in uninterrupted first strips (ST1), that are arranged in a first direction (x) in a first predetermined interval (a), and second strips (ST2), that are arranged in a second direction (y) in a second predetermined interval (b). The second strips (ST2) each comprise at least one interruption in a region between each two neighboring first strips (ST1) in form of a predetermined gap (d). Positively doped regions (P) and negatively doped regions (N) each are arranged as strips in parallel with the first strips (ST1) such that in a region between each two neighboring first strips (ST1) alternately either one of the positively doped regions (P) or one of the negatively doped regions (N) is arranged.

摘要翻译： 一种光电检测器，包括光栅（PC）。 光栅（PC）布置在有源半导体层的表面的顶部。 在不间断的第一条带（ST1）中以第一预定间隔（a）中的第一方向（x）布置光栅（PC），并且沿第二方向（y ）在第二预定间隔（b）中。 第二条带（ST2）各自包括形成预定间隙（d）的每个两个相邻的第一条带（ST1）之间的区域中的至少一个中断。 正掺杂区域（P）和负掺杂区域（N）各自被布置为与第一条带（ST1）平行的条带，使得在每两个相邻的第一条带（ST1）之间的区域中交替地将任一个正掺杂区域 P）或负掺杂区域（N）之一。

公开(公告)号：US20090055563A1

公开(公告)日：2009-02-26

申请号：US12259942

申请日：2008-10-28

申请人： James Stephen Fields, JR. ,  Paul Frank Lecocq ,  Brian Chan Monwai ,  Thomas Pflueger ,  Kevin Franklin Reick ,  Timothy M. Skergan ,  Scott Barnett Swaney

发明人： James Stephen Fields, JR. ,  Paul Frank Lecocq ,  Brian Chan Monwai ,  Thomas Pflueger ,  Kevin Franklin Reick ,  Timothy M. Skergan ,  Scott Barnett Swaney

IPC分类号： G06F13/42

CPC分类号： G06F15/161

摘要： In-band firmware executes instructions which cause commands to be sent on a coherency fabric. Fabric snoop logic monitors the coherency fabric for command packets that target a resource in one of the support chips attached via an FSI link. Conversion logic converts the information from the fabric packet into an FSI protocol. An FSI command is transmitted via the FSI transmit link to an FSI slave of the intended support chip. An FSI receive link receives response data from the FSI slave of the intended support chip. Conversion logic converts the information from the support chip received via the FSI receive link into the fabric protocol. Response packet generation logic generates the fabric response packet and returns it on the coherency fabric. An identical FSI link between a support processor and support chips allows direct access to the same resources on the support chips by out-of-band firmware.

摘要翻译： 带内固件执行指令，使指令在一致性结构上发送。 Fabric Snoop逻辑监视针对通过FSI链接附加的支持芯片之一的资源的命令包的一致性结构。 转换逻辑将信息从Fabric数据包转换为FSI协议。 FSI命令通过FSI传输链路发送到预期支持芯片的FSI从站。 FSI接收链路从预期的支持芯片的FSI从站接收响应数据。 转换逻辑将从通过FSI接收链路接收的支持芯片的信息转换为结构协议。 响应分组生成逻辑生成结构响应分组并将其返回到一致性结构上。 支持处理器和支持芯片之间的相同FSI链路允许通过带外固件直接访问支持芯片上的相同资源。

公开(公告)号：US20080276140A1

公开(公告)日：2008-11-06

申请号：US12042944

申请日：2008-03-05

申请人： Tobias Gemmeke ,  Christoph Jaeschke ,  Jens Kuenzer ,  Cedric Lichtenau ,  Thomas Pflueger ,  Jochen Preiss

发明人： Tobias Gemmeke ,  Christoph Jaeschke ,  Jens Kuenzer ,  Cedric Lichtenau ,  Thomas Pflueger ,  Jochen Preiss

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/318575

摘要： A semiconductor chip subdivided into power domains, at least one of the power domains is separately activated or deactivated and at least a part of the scannable storage elements are interconnected to one or more scan chains. At least one scan chain is serially subdivided into scan chain portions and the scan chain portion is arranged within one of the power domains. For at least one scan chain portion a bypass line is provided for passing by scan data and at least one select unit is provided for selecting between the bypass line and the corresponding scan chain portion in dependence of the activated or deactivated state of the corresponding power domains.

摘要翻译： 分为功率域的半导体芯片，至少一个功率域被单独激活或去激活，并且可扫描存储元件的至少一部分互连到一个或多个扫描链。 至少一个扫描链被连续地分成扫描链部分，并且扫描链部分被布置在一个功率域内。 对于至少一个扫描链部分，提供旁路线以通过扫描数据，并且提供至少一个选择单元用于根据相应功率域的激活或去激活状态在旁路线和对应的扫描链部分之间进行选择 。

公开(公告)号：US20080247415A1

公开(公告)日：2008-10-09

申请号：US12139631

申请日：2008-06-16

申请人： James Stephen Fields ,  Paul Frank Lecocq ,  Brian Chan Monwai ,  Thomas Pflueger ,  Kevin Franklin Reick ,  Timothy M. Skergan ,  Scott Barnett Swaney

发明人： James Stephen Fields ,  Paul Frank Lecocq ,  Brian Chan Monwai ,  Thomas Pflueger ,  Kevin Franklin Reick ,  Timothy M. Skergan ,  Scott Barnett Swaney

IPC分类号： H04L12/66

CPC分类号： G06F15/7842

摘要： A method and apparatus are provided for a support interface for memory-mapped resources. A support processor sends a sequence of commands over and FSI interface to a memory-mapped support interface on a processor chip. The memory-mapped support interface updates memory, memory-mapped registers or memory-mapped resources. The interface uses fabric packet generation logic to generate a single command packet in a protocol for the coherency fabric which consists of an address, command and/or data. Fabric commands are converted to FSI protocol and forwarded to attached support chips to access the memory-mapped resource, and responses from the support chips are converted back to fabric response packets. Fabric snoop logic monitors the coherency fabric and decodes responses for packets previously sent by fabric packet generation logic. The fabric snoop logic updates status register and/or writes response data to a read data register. The system also reports any errors that are encountered.

摘要翻译： 提供了一种用于存储器映射资源的支持接口的方法和装置。 支持处理器将一系列命令和FSI接口发送到处理器芯片上的存储器映射支持接口。 内存映射支持接口更新内存，内存映射寄存器或内存映射资源。 该接口使用结构数据包生成逻辑在由地址，命令和/或数据组成的一致性结构的协议中生成单个命令分组。 结构命令转换为FSI协议，并转发到附加的支持芯片以访问存储器映射的资源，并且来自支持芯片的响应被转换回到结构响应分组。 Fabric监听逻辑监视一致性结构，并解码先前由Fabric数据包生成逻辑发送的数据包的响应。 织物窥探逻辑更新状态寄存器和/或将响应数据写入读取数据寄存器。 系统还报告遇到的任何错误。