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公开(公告)号：US08285969B2
公开(公告)日：2012-10-09
申请号：US12552676
申请日：2009-09-02
IPC分类号： G06F12/06
CPC分类号： G06F12/0833 , G06F12/0831 , G06F12/1027 , Y02D10/13
摘要： Disclosed is an apparatus to reduce broadcasts in multiprocessors including a plurality of processors; a plurality of memory caches associated with the processors; a plurality of translation lookaside buffers (TLBs) associated with the processors; and a physical memory shared with the processors memory caches and TLBs; wherein each TLB includes a plurality of entries for translation of a page of addresses from virtual memory to physical memory, each TLB entry having page characterization information indicating whether the page is private to one processor or shared with more than one processor. Also disclosed is a computer program product and method to reduce broadcasts in multiprocessors.
摘要翻译： 公开了一种减少包括多个处理器在内的多处理器中的广播的装置; 与所述处理器相关联的多个存储器高速缓存; 与处理器相关联的多个翻译后备缓冲器（TLB）; 以及与处理器存储器高速缓存和TLB共享的物理存储器; 其中每个TLB包括用于将地址页从虚拟存储器翻译成物理存储器的多个条目，每个TLB条目具有指示该页面是一个处理器是专用还是与一个以上处理器共享的页面表征信息。 还公开了一种用于减少多处理器中的广播的计算机程序产品和方法。
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2.发明授权公开(公告)号：US07380047B2
公开(公告)日：2008-05-27
申请号：US10955780
申请日：2004-09-30
申请人： Philip George Emma , Allan Mark Hartstein , Thomas Roberts Puzak , Moinuddin Khalil Ahmed Qureshi
发明人： Philip George Emma , Allan Mark Hartstein , Thomas Roberts Puzak , Moinuddin Khalil Ahmed Qureshi
IPC分类号： G06F12/00
CPC分类号： G06F12/0848 , G06F12/0886 , G06F12/0897 , G06F12/127
摘要： A memory system and method includes a cache having a filtered portion and an unfiltered portion. The unfiltered portion is divided into block sized components, and the filtered portion is divided into sub-block sized components. Blocks evicted from the unfiltered portion have selected sub-blocks thereof cached in the filtered portion for servicing requests.
摘要翻译： 存储器系统和方法包括具有滤波部分和未滤波部分的高速缓存。 未过滤的部分被分成块大小的分量，并且滤波的部分被划分成子块大小的分量。 从未过滤部分移出的块具有缓存在过滤部分中的选定子块，用于维修请求。
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公开(公告)号：US20110191546A1
公开(公告)日：2011-08-04
申请号：US12700043
申请日：2010-02-04
摘要： An apparatus for memory access prediction which includes a plurality of processors, a plurality of memory caches associated with the processors, a plurality of saturation counters associated with the processors, each of the saturation counters having an indicator bit, and a physical memory shared with the processors, saturation counters and memory caches. Upon a cache miss for a data item, a cache snoop and access to physical memory are initiated in parallel for the data item if the indicator bit is a first predetermined bit (one (1) or zero (0)) whereas a cache snoop is initiated if the most significant bit is a second predetermined bit (zero (0) or one (1)).
摘要翻译： 一种用于存储器访问预测的装置，其包括多个处理器，与处理器相关联的多个存储器高速缓存，与处理器相关联的多个饱和计数器，每个饱和计数器具有指示符位，以及与该处理器共享的物理存储器 处理器，饱和度计数器和内存缓存。 在数据项的高速缓存未命中时，如果指示符位是第一预定位（一（1）或零（0）），则高速缓存监听和对物理存储器的访问被并行发起，而缓存窥探是 如果最高有效位是第二预定位（零（0）或1（1）），则启动。
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4.发明授权State machine based filtering of non-dominant branches to use a modified gshare scheme 有权基于状态机的非优势分支过滤使用修改的gshare方案公开(公告)号：US07747845B2
公开(公告)日：2010-06-29
申请号：US10844300
申请日：2004-05-12
CPC分类号： G06F9/3806 , G06F9/3848
摘要： Disclosed is a method and apparatus providing the ability to create a multi-level prediction algorithm, whereby branch predictions beyond the first level of prediction are maintained at a secondary level because the prior level was unsuccessfully able to highly predict the direction of the stated branch accurately. A secondary level is smaller in size than the upper level through selected filtering thereby enabling high prediction accuracy of branches while minimizing the amount of hardware required to perform stated predictions.
摘要翻译： 公开了一种提供创建多级预测算法的能力的方法和装置，其中超过第一级预测的分支预测保持在次级级别，因为先前级别不能成功地高度预测所述分支的方向 。 通过所选择的滤波，次级电平的尺寸小于上电平，从而能够实现分支的高预测精度，同时最小化执行所述预测所需的硬件量。
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公开(公告)号：US07337271B2
公开(公告)日：2008-02-26
申请号：US10724815
申请日：2003-12-01
申请人： Philip George Emma , Allan Mark Hartstein , Brian R. Prasky , Thomas Roberts Puzak , Moinuddin Khalil Ahmed Qureshi , Vijayalakshmi Srinivasan
发明人： Philip George Emma , Allan Mark Hartstein , Brian R. Prasky , Thomas Roberts Puzak , Moinuddin Khalil Ahmed Qureshi , Vijayalakshmi Srinivasan
CPC分类号： G06F9/3806
摘要： A memory storage structure includes a memory storage device, and a first meta-structure having a first size and operating at a first speed. The first speed is faster than a second speed for storing meta-information based on information stored in a memory. A second meta-structure is hierarchically associated with the first meta-structure. The second meta-structure has a second size larger than the first size and operates at the second speed such that faster and more accurate prefetching is provided by coaction of the first and second meta-structures. A method is provided to assemble the meta-information in the first meta-structure and copy this information to the second meta-structure, and prefetching the stored information from the second meta-structure to the first meta-structure ahead of its use.
摘要翻译： 存储器存储结构包括存储器存储设备和具有第一大小并以第一速度操作的第一元结构。 基于存储在存储器中的信息，第一速度比用于存储元信息的第二速度快。 第二个元结构与第一个元结构分层关联。 第二元结构具有大于第一尺寸的第二尺寸并且以第二速度操作，使得通过第一和第二元结构的共同作用来提供更快更准确的预取。 提供了一种用于在第一元结构中组装元信息并将该信息复制到第二元结构的方法，并且将其从第二元结构预取存储到其使用之前的第一元结构。
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公开(公告)号：US08627008B2
公开(公告)日：2014-01-07
申请号：US12700043
申请日：2010-02-04
摘要： An apparatus for memory access prediction which includes a plurality of processors, a plurality of memory caches associated with the processors, a plurality of saturation counters associated with the processors, each of the saturation counters having an indicator bit, and a physical memory shared with the processors, saturation counters and memory caches. Upon a cache miss for a data item, a cache snoop and access to physical memory are initiated in parallel for the data item if the indicator bit is a first predetermined bit (one (1) or zero (0)) whereas a cache snoop is initiated if the most significant bit is a second predetermined bit (zero (0) or one (1)).
摘要翻译： 一种用于存储器访问预测的装置，其包括多个处理器，与处理器相关联的多个存储器高速缓存，与处理器相关联的多个饱和计数器，每个饱和计数器具有指示符位，以及与该处理器共享的物理存储器 处理器，饱和度计数器和内存缓存。 在数据项的高速缓存未命中时，如果指示符位是第一预定位（一（1）或零（0）），则高速缓存监听和对物理存储器的访问被并行发起，而缓存窥探是 如果最高有效位是第二预定位（零（0）或1（1）），则启动。
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公开(公告)号：US20110055515A1
公开(公告)日：2011-03-03
申请号：US12552676
申请日：2009-09-02
IPC分类号： G06F12/06
CPC分类号： G06F12/0833 , G06F12/0831 , G06F12/1027 , Y02D10/13
摘要： Disclosed is an apparatus to reduce broadcasts in multiprocessors including a plurality of processors; a plurality of memory caches associated with the processors; a plurality of translation lookaside buffers (TLBs) associated with the processors; and a physical memory shared with the processors memory caches and TLBs; wherein each TLB includes a plurality of entries for translation of a page of addresses from virtual memory to physical memory, each TLB entry having page characterization information indicating whether the page is private to one processor or shared with more than one processor. Also disclosed is a computer program product and method to reduce broadcasts in multiprocessors.
摘要翻译： 公开了一种减少包括多个处理器在内的多处理器中的广播的装置; 与所述处理器相关联的多个存储器高速缓存; 与处理器相关联的多个翻译后备缓冲器（TLB）; 以及与处理器存储器高速缓存和TLB共享的物理存储器; 其中每个TLB包括用于将地址页从虚拟存储器翻译成物理存储器的多个条目，每个TLB条目具有指示该页面是一个处理器是专用还是与一个以上处理器共享的页面表征信息。 还公开了一种用于减少多处理器中的广播的计算机程序产品和方法。
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8.发明申请公开(公告)号：US20080215816A1
公开(公告)日：2008-09-04
申请号：US12116615
申请日：2008-05-07
申请人： Philip George Emma , Allan Mark Hartstein , Thomas Roberts Puzak , Moinuddin Khalil Ahmed Qureshi
发明人： Philip George Emma , Allan Mark Hartstein , Thomas Roberts Puzak , Moinuddin Khalil Ahmed Qureshi
IPC分类号： G06F12/08
CPC分类号： G06F12/0848 , G06F12/0886 , G06F12/0897 , G06F12/127
摘要： A memory system and method includes a cache having a filtered portion and an unfiltered portion. The unfiltered portion is divided into block sized components, and the filtered portion is divided into sub-block sized components. Blocks evicted from the unfiltered portion have selected sub-blocks thereof cached in the filtered portion for servicing requests.
摘要翻译： 存储器系统和方法包括具有滤波部分和未滤波部分的高速缓存。 未过滤的部分被分成块大小的分量，并且滤波的部分被划分成子块大小的分量。 从未过滤部分移出的块具有缓存在过滤部分中的选定子块，用于维修请求。
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公开(公告)号：US07657726B2
公开(公告)日：2010-02-02
申请号：US11923902
申请日：2007-10-25
申请人： Philip George Emma , Allan Mark Hartstein , Brian R. Prasky , Thomas Roberts Puzak , Moinuddin Khalil Ahmed Qureshi , Vijayalakshmi Srinivasan
发明人： Philip George Emma , Allan Mark Hartstein , Brian R. Prasky , Thomas Roberts Puzak , Moinuddin Khalil Ahmed Qureshi , Vijayalakshmi Srinivasan
IPC分类号： G06F9/312
CPC分类号： G06F9/3806
摘要： A memory storage structure includes a memory storage device, and a first meta-structure having a first size and operating at a first speed. The first speed is faster than a second speed for storing meta-information based on information stored in a memory. A second meta-structure is hierarchically associated with the first meta-structure. The second meta-structure has a second size larger than the first size and operates at the second speed such that faster and more accurate prefetching is provided by coaction of the first and second meta-structures. A method is provided to assemble the meta-information in the first meta-structure and copy this information to the second meta-structure, and prefetching the stored information from the second meta-structure to the first meta-structure ahead of its use.
摘要翻译： 存储器存储结构包括存储器存储设备和具有第一大小并以第一速度操作的第一元结构。 基于存储在存储器中的信息，第一速度比用于存储元信息的第二速度快。 第二个元结构与第一个元结构分层关联。 第二元结构具有大于第一尺寸的第二尺寸并且以第二速度操作，使得通过第一和第二元结构的共同作用来提供更快更准确的预取。 提供了一种用于在第一元结构中组装元信息并将该信息复制到第二元结构的方法，并且将其从第二元结构预取存储到其使用之前的第一元结构。
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