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    Thermal cycling and gradient management in three-dimensional stacked architectures
    1.
    发明授权
    Thermal cycling and gradient management in three-dimensional stacked architectures 有权
    三维堆叠架构中的热循环和梯度管理

    公开(公告)号：US08489217B2

    公开(公告)日：2013-07-16

    申请号：US12984096

    申请日：2011-01-04

    Applicant: Chen-Yong Cher ,  Wilfried E. Haensch ,  Eren Kursun ,  David R. Motschman

    Inventor： Chen-Yong Cher ,  Wilfried E. Haensch ,  Eren Kursun ,  David R. Motschman

    IPC: G06F19/00

    CPC classification number: G06F1/3234 ,  G06F1/206

    Abstract: A mechanism is provided for minimizing reliability problems in a three-dimensional (3D) integrated circuit. A set of sensors are interrogated for current data. A direction of force and a magnitude of the force are determined based on the current data for each sensor in the set of sensors for each of one or more directions between the sensor and at least one neighboring sensor thereby forming a set of forces. Each of the set of forces is used to identify one or more points of stress that are at or above the predetermined force threshold. Responsive to identifying at least one point of stress that is at or above the predetermined force threshold, one or more temperature actuation actions are initiated in order to reduce at least one point of stress in the region where the at least one point of stress is identified.

    Abstract translation: 提供了一种用于最小化三维（3D）集成电路中的可靠性问题的机制。 一组传感器被询问用于当前数据。 基于用于传感器和至少一个相邻传感器之间的一个或多个方向中的每一个的传感器组中的每个传感器的当前数据来确定力的方向和力的大小，从而形成一组力。 所述一组力中的每一个用于识别处于或高于预定力阈值的一个或多个应力点。 响应于识别处于或高于预定力阈值的至少一个应力点，启动一个或多个温度致动动作，以便在识别出至少一个应力点的区域中减少至少一个应力点 。

    MEMORY MODULE CONNECTOR HAVING MEMORY MODULE COOLING STRUCTURES
    5.
    发明申请
    MEMORY MODULE CONNECTOR HAVING MEMORY MODULE COOLING STRUCTURES 有权
    具有存储模块冷却结构的存储模块连接器

    公开(公告)号：US20110286179A1

    公开(公告)日：2011-11-24

    申请号：US12786067

    申请日：2010-05-24

    Applicant: David R. Motschman ,  Mark E. Steinke ,  Aparna Vallury

    Inventor： David R. Motschman ,  Mark E. Steinke ,  Aparna Vallury

    IPC: G06F1/20

    CPC classification number: G06F1/20 ,  H01L23/3672 ,  H01L23/3675 ,  H01L23/4093 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: One embodiment of the present invention provides a computer memory system that includes at least one DIMM connector having a DIMM socket for releasably receiving a terminal edge of a DIMM. A metallic or otherwise highly heat-conductive base is secured to the DIMM connector. A pair of heat spreaders is secured to the base on opposing sides of the DIMM socket. Each heat spreader includes a DIMM-engagement portion spaced from the base. The heat spreaders are nondestructively moveable between an open position spaced apart for receiving the DIMM between the heat spreaders and a closed position for thermally engaging opposing faces of the DIMM. The heat spreaders provide a continuous thermally-conductive pathway between the DIMM-engagement portion and the base. Heatsink fins extend laterally from the base to provide cooling.

    Abstract translation: 本发明的一个实施例提供了一种计算机存储器系统，其包括具有用于可释放地接收DIMM的终端边缘的DIMM插槽的至少一个DIMM连接器。 金属或其他高度导热的基座固定到DIMM连接器。 一对散热器在DIMM插槽的相对侧固定到基座。 每个散热器包括与基座间隔开的DIMM接合部分。 散热器在间隔开的开放位置之间是非破坏性的，以在散热器之间接收DIMM，并且用于热接合DIMM的相对面的闭合位置。 散热器在DIMM接合部分和基座之间提供连续的导热通路。 散热片从基座横向延伸以提供冷却。

    Methods, Systems, and Computer Program Products for Implementing Spread Spectrum Using Digital Signal Processing Techniques
    6.
    发明申请
    Methods, Systems, and Computer Program Products for Implementing Spread Spectrum Using Digital Signal Processing Techniques 审中-公开
    使用数字信号处理技术实现扩频的方法，系统和计算机程序产品

    公开(公告)号：US20090147827A1

    公开(公告)日：2009-06-11

    申请号：US11951726

    申请日：2007-12-06

    Applicant: Richard Holmquist ,  Jordan R. Keuseman ,  David R. Motschman ,  George R. Zettles, IV

    Inventor： Richard Holmquist ,  Jordan R. Keuseman ,  David R. Motschman ,  George R. Zettles, IV

    IPC: H04B1/69

    CPC classification number: G06F1/08

    Abstract: Implementing spread spectrum using digital signal processing techniques. An incoming clock signal is received and sampled using a programmable sampling mechanism to generate a plurality of signal data points included in a sampled signal. The sampled signal is conditioned using a programmable signal conditioning mechanism capable of performing at least one of: reducing a cycle to cycle jitter of the sampled signal; or adjusting the sampled signal to a base frequency. The signal data points are processed and spread across a band of frequencies using a programmable digital signal processor to adjust at least one of: (a) an amplitude, (b) a phase shift, or (c) a frequency shift; for each of a plurality of respective signal data points at a plurality of corresponding frequencies in the band of frequencies. An output waveform is constructed from the processed and spread signal data points, wherein the output waveform constitutes a clock output signal.

    Abstract translation: 使用数字信号处理技术实现扩频。 使用可编程采样机构接收和采样输入时钟信号，以产生包括在采样信号中的多个信号数据点。 使用可执行以下中的至少一个的可编程信号调节机构调节采样信号：减少采样信号的周期抖动周期; 或将采样信号调整到基频。 信号数据点使用可编程数字信号处理器在频带上进行处理和扩展，以调整以下至少一个：（a）幅度，（b）相移或（c）频移; 对于频率带中的多个相应频率的多个相应信号数据点中的每一个。 输出波形由处理和扩展的信号数据点构成，其中输出波形构成时钟输出信号。

    Method and system for internal layer-layer thermal enhancement
    8.
    发明授权
    Method and system for internal layer-layer thermal enhancement 有权
    内层热增强方法和系统

    公开(公告)号：US08367478B2

    公开(公告)日：2013-02-05

    申请号：US13151672

    申请日：2011-06-02

    Applicant: Gerald K. Bartley ,  Charles L. Johnson ,  John E. Kelly, III ,  David R. Motschman

    Inventor： Gerald K. Bartley ,  Charles L. Johnson ,  John E. Kelly, III ,  David R. Motschman

    IPC: H01L21/50 ,  H01L21/48 ,  H01L23/34 ,  H01L23/52 ,  H01L23/48 ,  H01L23/40 ,  H01L23/538

    CPC classification number: H01L29/0657 ,  H01L23/3677 ,  H01L23/4275 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06589

    Abstract: The exemplary embodiments of the present invention provide a method and apparatus for enhancing the cooling of a chip stack of semiconductor chips. The method includes creating a first chip with circuitry on a first side and creating a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The method further includes creating a cavity in a second side of the first chip between the connectors and filling the cavity with a thermal material. The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The apparatus further includes wherein portions of a second side of the first chip between the connectors is removed to provide a cavity in which a thermal material is placed.

    Abstract translation: 本发明的示例性实施例提供了一种用于增强半导体芯片的芯片堆叠的冷却的方法和装置。 该方法包括在第一侧上创建具有电路的第一芯片，并通过连接器网格将第二芯片电连接并机械耦合到第一芯片。 该方法还包括在连接器之间的第一芯片的第二侧中形成空腔，并用热材料填充空腔。 具有增强的冷却装置的半导体芯片的芯片堆叠包括具有第一侧上的电路的第一芯片和通过连接器格栅电和机械地耦合到第一芯片的第二芯片。 该装置还包括：其中，连接器之间的第一芯片的第二侧的部分被去除以提供放置热材料的空腔。

    Thermal Cycling and Gradient Management in Three-Dimensional Stacked Architectures
    9.
    发明申请
    Thermal Cycling and Gradient Management in Three-Dimensional Stacked Architectures 有权
    三维堆叠架构中的热循环和梯度管理

    公开(公告)号：US20120173036A1

    公开(公告)日：2012-07-05

    申请号：US12984096

    申请日：2011-01-04

    Applicant: Chen-Yong Cher ,  Wilfried E. Haensch ,  Eren Kursun ,  David R. Motschman

    Inventor： Chen-Yong Cher ,  Wilfried E. Haensch ,  Eren Kursun ,  David R. Motschman

    IPC: G05D23/19

    CPC classification number: G06F1/3234 ,  G06F1/206

    Abstract: A mechanism is provided for minimizing reliability problems in a three-dimensional (3D)) integrated circuit. A set of sensors are interrogated for current data. A direction of force and a magnitude of the force are determined based on the current data for each sensor in the set of sensors for each of one or more directions between the sensor and at least one neighboring sensor thereby forming a set of forces. Each of the set of forces is used to identify one or more points of stress that are at or above the predetermined force threshold. Responsive to identifying at least one point of stress that is at or above the predetermined force threshold, one or more temperature actuation actions are initiated in order to reduce at least one point of stress in the region where the at least one point of stress is identified.

    Abstract translation: 提供了用于最小化三维（3D））集成电路中的可靠性问题的机制。 一组传感器被询问用于当前数据。 基于用于传感器和至少一个相邻传感器之间的一个或多个方向中的每一个的传感器组中的每个传感器的当前数据来确定力的方向和力的大小，从而形成一组力。 所述一组力中的每一个用于识别处于或高于预定力阈值的一个或多个应力点。 响应于识别处于或高于预定力阈值的至少一个应力点，启动一个或多个温度致动动作，以便在识别出至少一个应力点的区域中减少至少一个应力点 。

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