Invention Grant
US08635487B2 Memory interface having extended strobe burst for write timing calibration
有权
存储器接口具有用于写时序校准的扩展选通脉冲串
- Patent Title: Memory interface having extended strobe burst for write timing calibration
- Patent Title (中): 存储器接口具有用于写时序校准的扩展选通脉冲串
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Application No.: US12723843Application Date: 2010-03-15
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Publication No.: US08635487B2Publication Date: 2014-01-21
- Inventor: Kevin C. Gower , Kyu-hyoun Kim
- Applicant: Kevin C. Gower , Kyu-hyoun Kim
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Patterson & Sheridan LLP
- Main IPC: H03M13/00
- IPC: H03M13/00 ; G06F13/00 ; G06F3/00 ; G11C8/00
Abstract:
Methods and systems for calibrating parameters for communication between a controller and a memory device. A memory controller may be configured to calibrate one or more of the write latency and/or the latency window of a memory device such that a data signal and a data strobe signal are received by the memory device within the latency window of the memory device.
Public/Granted literature
- US20110225444A1 MEMORY INTERFACE HAVING EXTENDED STROBE BURST FOR WRITE TIMING CALIBRATION Public/Granted day:2011-09-15
Information query
IPC分类:
