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    SEMICONDUCTOR DEVICE
    1.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20250151259A1

    公开(公告)日：2025-05-08

    申请号：US18657885

    申请日：2024-05-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hongjun Lee ,  Keunnam Kim ,  Kiseok Lee

    IPC: H10B12/00 ,  G11C11/16 ,  G11C11/4091

    Abstract: Provided is a semiconductor device including a first word line extending in a first direction, bit lines extending in a second direction different from the first direction in a plan view, a second word line between ones of the bit lines and extending in the second direction, and a first memory cell. The first memory cell may include a first transistor electrically connected to a first one of the bit lines and the first word line, a second transistor electrically connected to the second word line and including source/drain electrodes, and a capacitor electrically connected to the second transistor. One of the source/drain electrodes of the second transistor may be electrically connected to the first transistor.

    Methods of manufacturing semiconductor devices
    2.
    发明授权
    Methods of manufacturing semiconductor devices 有权

    公开(公告)号：US12237265B2

    公开(公告)日：2025-02-25

    申请号：US18321917

    申请日：2023-05-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sangoh Park ,  Dongjun Lee ,  Keunnam Kim ,  Seunghune Yang

    IPC: H01L21/768 ,  H01L21/02 ,  H01L23/528 ,  H01L29/786 ,  H10B12/00

    Abstract: A semiconductor device may include a substrate including a cell region and a core/peripheral region. A plurality of bit line structures may be in the cell region of the substrate. A gate structure may be in the core/peripheral regions of the substrate. A lower contact plug and an upper contact plug may be between the bit line structures. The lower contact plug and the upper contact plug may be stacked in a vertical direction. A landing pad pattern may contact an upper sidewall of the upper contact plug. The landing pad pattern may be between an upper portion of the upper contact plug and an upper portion of one of the bit line structures. An upper surface of the landing pad pattern may be higher than an upper surface of each of the bit line structures. A peripheral contact plug may be formed in the core/peripheral regions of the substrate. A wiring may be electrically connected to an upper surface of the peripheral contact plug.

    SEMICONDUCTOR MEMORY DEVICE
    3.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20240357801A1

    公开(公告)日：2024-10-24

    申请号：US18530342

    申请日：2023-12-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hanjin Lim ,  Jinwoo Han ,  Kiseok Lee ,  Keunnam Kim ,  Seokhan Park ,  Moonyoung Jeong

    IPC: H10B12/00 ,  H01L21/28 ,  H01L29/51

    CPC classification number: H10B12/482 ,  H01L29/40111 ,  H01L29/516 ,  H10B12/315 ,  H10B12/488 ,  H10B12/50

    Abstract: A semiconductor memory device includes a bit line extending in a first direction, an active pattern on the bit line, the active pattern including first and second vertical portions facing each other in the first direction and a horizontal portion connecting the first and second vertical portions, first and second word lines on the horizontal portion between the first and second vertical portions, the first and second word lines extending in a second direction crossing the first direction, a gate insulating pattern between the first and second word lines and the active pattern, and a capacitor connected to each of the first and second vertical portions, the capacitor including a first electrode pattern connected to one of the first and second vertical portions, a second electrode pattern on the first electrode pattern, and a ferroelectric pattern between the first electrode pattern and the second electrode pattern.

    SEMICONDUCTOR DEVICES
    5.
    发明公开
    SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20230309293A1

    公开(公告)日：2023-09-28

    申请号：US18327920

    申请日：2023-06-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： HYOSUB KIM ,  Keunnam Kim ,  Manbok Kim ,  Soojeong Kim ,  Chulkwon Park ,  Seungbae Jeon ,  Yoosang Hwang

    IPC: H10B12/00

    CPC classification number: H10B12/315 ,  H10B12/34 ,  H10B12/053 ,  H10B12/0335 ,  H10B12/482

    Abstract: Semiconductor devices may include an active pattern, a gate structure in an upper portion of the active pattern, a bit line structure on the active pattern, a lower spacer structure on a lower portion of a sidewall of the bit line structure, and an upper spacer structure on an upper portion of the sidewall of the bit line structure. The lower spacer structure includes first and second lower spacers sequentially stacked, the first lower spacer contacts the lower portion of the sidewall of the bit line structure and does not include nitrogen, and the second lower spacer includes a material different from the first lower spacer. A portion of the upper spacer structure contacting the upper portion of the sidewall of the bit line structure includes a material different from the first lower spacer.

    Semiconductor memory devices having protruding contact portions
    6.
    发明授权
    Semiconductor memory devices having protruding contact portions 有权

    公开(公告)号：US11723191B2

    公开(公告)日：2023-08-08

    申请号：US17192084

    申请日：2021-03-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Minsu Choi ,  Myeong-Dong Lee ,  Hyeon-Woo Jang ,  Keunnam Kim ,  Sooho Shin ,  Yoosang Hwang

    IPC: H10B12/00

    CPC classification number: H10B12/34 ,  H10B12/0335 ,  H10B12/053 ,  H10B12/315

    Abstract: Disclosed are a semiconductor memory device and a method of fabricating the same. The device includes a substrate including an active pattern with doped regions, a gate electrode crossing the active pattern between the doped regions, a bit line crossing the active pattern and being electrically connected to one of the doped regions, a spacer on a side surface of the bit line, a first contact coupled to another of the doped regions and spaced apart from the bit line with the spacer interposed therebetween, a landing pad on the first contact, and a data storing element on the landing pad. The another of the doped regions has a top surface, an upper side surface, and a curved top surface that extends from the top surface to the upper side surface. The first contact is in contact with the curved top surface and the upper side surface.

    SEMICONDUCTOR AND MANUFACTURING METHOD OF THE SAME
    9.
    发明申请
    SEMICONDUCTOR AND MANUFACTURING METHOD OF THE SAME 有权

    公开(公告)号：US20210066305A1

    公开(公告)日：2021-03-04

    申请号：US16896470

    申请日：2020-06-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyosub Kim ,  Keunnam Kim ,  Dongoh Kim ,  Bongsoo Kim ,  Euna Kim ,  Chansic Yoon ,  Kiseok Lee ,  Hyeonok Jung ,  Sunghee Han ,  Yoosang Hwang

    IPC: H01L27/108 ,  H01L23/528

    Abstract: A semiconductor device includes: an active region defined by a device isolation layer formed in a substrate; a word line configured to cross the active region, the word line extending in a first direction and being formed in the substrate; a bit line extending in a second direction perpendicular to the first direction on the word line; a first contact connecting the bit line to the active region; a first mask for forming the active region, the first mask being formed on the active region; and a second mask of which a height of a top surface thereof is greater than a height of a top surface of the active region, the second mask covering the word line, wherein the active region has a bar shape that extends to form an acute angle with respect to the first direction.

    Semiconductor devices and methods of fabricating the same
    10.
    发明授权
    Semiconductor devices and methods of fabricating the same 有权

    公开(公告)号：US10796950B2

    公开(公告)日：2020-10-06

    申请号：US16238172

    申请日：2019-01-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Myeong-Dong Lee ,  Keunnam Kim ,  Dongryul Lee ,  Minseong Choi ,  Jimin Choi ,  Yong Kwan Kim ,  Changhyun Cho ,  Yoosang Hwang

    IPC: H01L21/76 ,  H01L21/768 ,  H01L27/108 ,  H01L23/532 ,  H01L23/535

    Abstract: According to some embodiments, a semiconductor device may include gate structures on a substrate; first and second impurity regions formed in the substrate and at both sides of each of the gate structures; conductive line structures provided to cross the gate structures and connected to the first impurity regions; and contact plugs connected to the second impurity regions, respectively. For each of the conductive line structures, the semiconductor device may include a first air spacer provided on a sidewall of the conductive line structure; a first material spacer provided between the conductive line structure and the first air spacer; and an insulating pattern provided on the air spacer. The insulating pattern may include a first portion and a second portion, and the second portion may have a depth greater than that of the first portion and defines a top surface of the air spacer.

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