公开(公告)号：US20230070835A1

公开(公告)日：2023-03-09

申请号：US17724901

申请日：2022-04-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hongjun Lee ,  Kang-Uk Kim ,  Hoouk Lee

IPC: H01L27/108

Abstract: A semiconductor device may include a substrate including a cell region and a peripheral region, bit lines on the cell region and extending in a first direction parallel to a top surface of the substrate, a lower capping pattern on a top surface of each of the bit lines, a bit line spacer on a side surface of each of the bit lines and extending to a side surface of the lower capping pattern, and a respective upper capping pattern on a top surface of the lower capping pattern. The respective upper capping pattern is on at least a portion of a top surface of the bit line spacer.

公开(公告)号：US20250098146A1

公开(公告)日：2025-03-20

申请号：US18815974

申请日：2024-08-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hongjun Lee ,  Kiseok Lee ,  Huijung Kim ,  Younggeun Song ,  Yongjin Lee

IPC: H10B12/00

Abstract: A semiconductor device includes bit lines, channels, a first capping pattern, a gate insulation pattern, a gate electrode and capacitors. The bit lines are on a substrate, and each of the bit lines extends in a first direction. The bit lines are spaced apart from each other in a second direction. The channels are spaced apart from each other in the first direction. The first capping pattern is on a sidewall of each of the channels. The gate insulation pattern is on a sidewall of the first capping pattern. The gate electrode is on a sidewall of the gate insulation pattern. The capacitors are electrically connected to respective ones of the channels.

公开(公告)号：US20240224507A1

公开(公告)日：2024-07-04

申请号：US18541625

申请日：2023-12-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongmin Kim ,  Taejin Park ,  Chansic Yoon ,  Kiseok Lee ,  Hongjun Lee

IPC: H10B12/00 ,  H01L29/417 ,  H01L29/423

CPC classification number: H10B12/34 ,  H01L29/41741 ,  H01L29/4236 ,  H10B12/315

Abstract: A semiconductor device includes an active pattern on a substrate, a gate structure, a conductive filling pattern and a bit line structure on the conductive filling pattern. The gate structure extends through an upper portion of the active pattern, and has an upper surface higher than an upper surface of the active pattern. The conductive filling pattern includes a lower portion on the active pattern and an upper portion thereon. The lower portion contacts an upper sidewall of the gate structure, and the upper portion has a width greater than a width of the lower portion.

公开(公告)号：US20250081448A1

公开(公告)日：2025-03-06

申请号：US18672227

申请日：2024-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungmuk Kim ,  Kiseok Lee ,  Keunnam Kim ,  Hongjun Lee

IPC: H10B12/00

Abstract: A semiconductor device includes a first gate structure in a cell region of a substrate, where the substrate includes a peripheral circuit region, a bit line structure on the cell region of the substrate, a cell capacitor structure on the bit line structure, a decoupling capacitor structure on the peripheral circuit region of the substrate, and a second gate structure on the decoupling capacitor structure.

公开(公告)号：US20240407150A1

公开(公告)日：2024-12-05

申请号：US18737605

申请日：2024-06-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sukhwa Jang ,  Kanguk Kim ,  Hyunsuk Noh ,  Yeongshin Park ,  Sangkyu Sun ,  Sunyoung Lee ,  Sohyang Lee ,  Hongjun Lee ,  Hosun Jung ,  Jeongmin Jin ,  Jeonghee Choi ,  Jinseo Choi ,  Cera Hong

IPC: H10B12/00

Abstract: A method of manufacturing a semiconductor device includes forming a lower structure including a plurality of transistors, forming a conductive layer on the lower structure, forming first preliminary pad mask patterns and wiring mask patterns on the conductive layer, forming pad mask patterns by patterning the first preliminary pad mask patterns while protecting the wiring mask patterns, and etching the conductive layer using the pad mask patterns and the wiring mask patterns as an etching mask to form pad patterns and wiring patterns.

公开(公告)号：US20250071969A1

公开(公告)日：2025-02-27

申请号：US18623816

申请日：2024-04-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yun Choi ,  Seungmuk Kim ,  Inwoo Kim ,  Sohyun Park ,  Hanseong Shin ,  Kiseok Lee ,  Hyunjin Lee ,  Hosang Lee ,  Hongjun Lee ,  Heejae Chae

IPC: H10B12/00 ,  H01L21/027 ,  H01L21/311

Abstract: A semiconductor device may include a plurality of active patterns disposed on a substrate, a gate structure extending in a first direction, a bit line structure extending in a second direction, and a plurality of capacitors electrically connected to the plurality of active patterns, respectively, the plurality of active patterns having a shape extending in a third direction oblique to the first and second directions, the gate structure passing through centers of the plurality of active patterns, the bit line structure connected to first end portions of the plurality of active patterns, the plurality of capacitors connected to second end portions of the plurality of active patterns, respectively, the first end portion and the second end portion positioned at opposite sides with respect to the gate structure, and the first end portion and the second end portion having point-symmetrical shapes with respect to a center of the active pattern.

公开(公告)号：US12022645B2

公开(公告)日：2024-06-25

申请号：US17398136

申请日：2021-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sukhwa Jang ,  Kanguk Kim ,  Hyunsuk Noh ,  Yeongshin Park ,  Sangkyu Sun ,  Sunyoung Lee ,  Sohyang Lee ,  Hongjun Lee ,  Hosun Jung ,  Jeongmin Jin ,  Jeonghee Choi ,  Jinseo Choi ,  Cera Hong

IPC: H10B12/00

CPC classification number: H10B12/0335 ,  H10B12/053 ,  H10B12/09 ,  H10B12/315 ,  H10B12/34 ,  H10B12/50

Abstract: A method of manufacturing a semiconductor device includes forming a lower structure including a plurality of transistors, forming a conductive layer on the lower structure, forming first preliminary pad mask patterns and wiring mask patterns on the conductive layer, forming pad mask patterns by patterning the first preliminary pad mask patterns while protecting the wiring mask patterns, and etching the conductive layer using the pad mask patterns and the wiring mask patterns as an etching mask to form pad patterns and wiring patterns.