公开(公告)号：US20170133263A1

公开(公告)日：2017-05-11

申请号：US15342456

申请日：2016-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungseok MIN ,  Moojin KIM ,  Seongjin NAM ,  Sughyun SUNG ,  YoungHoon SONG ,  Youngmook OH

IPC: H01L21/762 ,  H01L21/3065 ,  H01L21/02

CPC classification number: H01L21/76224 ,  H01J2237/3347 ,  H01L21/02118 ,  H01L21/3065 ,  H01L21/31116 ,  H01L27/10879

Abstract: A method of fabricating a semiconductor device may include forming trenches in a substrate to define a fin structure extending in a direction, forming a device isolation layer to fill the trenches, and removing an upper portion of the device isolation layer to expose an upper side surface of the fin structure. The exposing of the upper side surface of the fin structure may include repeatedly performing an etching cycle including a first step and a second step, and an etching rate of the device isolation layer to the fin structure may be higher in the second step than in the first step.

公开(公告)号：US20170236921A1

公开(公告)日：2017-08-17

申请号：US15390754

申请日：2016-12-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungseok MIN ,  Seongjin NAM ,  Sughyun SUNG ,  Youngmook OH ,  Migyeong GWON ,  Hyungdong KIM ,  InWon PARK ,  Hyunggoo LEE

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/06 ,  H01L23/535 ,  H01L29/08 ,  H01L21/683 ,  H01L29/161 ,  H01L29/165 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/311 ,  H01L29/78 ,  H01L29/16

CPC classification number: H01L29/66795 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/6833 ,  H01L23/535 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7848 ,  H01L29/7851

Abstract: A semiconductor device includes a fin structure which vertically protrudes from a substrate and extends in a first direction parallel to a top surface of the substrate. The fin structure includes a lower pattern and an active pattern vertically protruding from a top surface of the lower pattern. The top surface of the lower pattern includes a flat portion substantially parallel to the top surface of the substrate. The lower pattern includes a first sidewall extending in the first direction and a second sidewall extending in a second direction crossing the first direction. The first sidewall is inclined relative to the top surface of the substrate at a first angle greater than a second angle corresponding to the second sidewall that is inclined relative to the top surface of the substrate.

公开(公告)号：US20170025511A1

公开(公告)日：2017-01-26

申请号：US15189312

申请日：2016-06-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chul Woong LEE ,  Hanseung KWAK ,  Youngmook OH

IPC: H01L29/423 ,  H01L21/8234 ,  H01L27/11 ,  H01L29/06 ,  H01L27/088

CPC classification number: H01L21/823481 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823468 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/1104 ,  H01L29/0649

Abstract: Semiconductor devices and methods of fabricating the same are provided. The semiconductor devices may include gate electrodes on a substrate. A longitudinal direction of each of the gate electrodes may extend in a first direction, and ones of the gate electrodes may be arranged in the first direction. The semiconductor devices may also include first and second gate spacers extending in the first direction and on respective sidewalls of the ones of the gate electrodes. The first and second gate spacers may be spaced apart from each other in a second direction that is different from the first direction. The semiconductor devices may further include gate separation patterns, and ones of the gate separation patterns may be between two among the ones of the gate electrodes adjacent to each other in the first direction and between the first and second gate spacers.

Abstract translation: 提供半导体器件及其制造方法。 半导体器件可以在衬底上包括栅电极。 每个栅电极的纵向方向可以在第一方向上延伸，并且栅电极中的一个可以沿第一方向布置。 半导体器件还可以包括在第一方向上延伸的第一和第二栅极间隔件以及栅极电极的相应侧壁。 第一和第二栅极间隔物可以在不同于第一方向的第二方向上彼此间隔开。 半导体器件还可以包括栅极分离图案，并且栅极分离图案中的一个可以在第一方向上彼此相邻的栅电极中的两个之间以及第一和第二栅极间隔物之间​​。

公开(公告)号：US20180151447A1

公开(公告)日：2018-05-31

申请号：US15882190

申请日：2018-01-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chul Woong LEE ,  Hanseung KWAK ,  Youngmook OH

IPC: H01L21/8234 ,  H01L29/06 ,  H01L27/11

CPC classification number: H01L21/823481 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823468 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/1104 ,  H01L29/0649

Abstract: Semiconductor devices and methods of fabricating the same are provided. The semiconductor devices may include gate electrodes on a substrate. A longitudinal direction of each of the gate electrodes may extend in a first direction, and ones of the gate electrodes may be arranged in the first direction. The semiconductor devices may also include first and second gate spacers extending in the first direction and on respective sidewalls of the ones of the gate electrodes. The first and second gate spacers may be spaced apart from each other in a second direction that is different from the first direction. The semiconductor devices may further include gate separation patterns, and ones of the gate separation patterns may be between two among the ones of the gate electrodes adjacent to each other in the first direction and between the first and second gate spacers.

公开(公告)号：US20180145082A1

公开(公告)日：2018-05-24

申请号：US15635583

申请日：2017-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungsoo HONG ,  JeongYun LEE ,  GeumJung SEONG ,  HyunHo JUNG ,  Minchan GWAK ,  Kyungseok MIN ,  Youngmook OH ,  Jae-Hoon WOO ,  Bora LIM

IPC: H01L27/11 ,  H01L29/06

CPC classification number: H01L27/1108 ,  H01L21/823821 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/0649

Abstract: A semiconductor device includes a first active pattern and a second active pattern on a substrate, a first gate electrode and a second gate electrode respectively across the first active pattern and the second active pattern, a first insulation pattern between and separating the first and second gate electrodes, a gate spacer on a sidewall of the first gate electrode, on a sidewall of the second gate electrode, and on a sidewall of the first insulation pattern, and a second insulation pattern between the gate spacer and the sidewall of the first insulation pattern, wherein the first gate electrode, the first insulation pattern, and the second gate electrode are arranged along a first direction, and wherein the gate spacer extends in the first direction.

公开(公告)号：US20220189970A1

公开(公告)日：2022-06-16

申请号：US17392377

申请日：2021-08-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Haegeon JUNG ,  Taeyong KWON ,  Kwang-Yong YANG ,  Youngmook OH ,  Bokyoung LEE ,  Seung Mo HA ,  Hyunggoo LEE

IPC: H01L27/11 ,  H01L27/088 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

Abstract: A semiconductor device includes a substrate having a first memory cell and a second memory cell, the first and second memory cells being adjacent to each other in a first direction, first to fourth memory fins adjacent to each other in the first direction in the first memory cell, the first to fourth memory fins protruding from the substrate, fifth to eighth memory fins adjacent to each other in the first direction in the second memory cell, the fifth to eighth memory fins protruding from the substrate, and a first shallow device isolation layer between the fourth memory fin and the fifth memory fin, a sidewall of the first shallow device isolation layer having an inflection point.

公开(公告)号：US20210296254A1

公开(公告)日：2021-09-23

申请号：US17338787

申请日：2021-06-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hongsik SHIN ,  Sanghyun LEE ,  Hakyoon AHN ,  Seonghan OH ,  Youngmook OH

IPC: H01L23/532 ,  H01L21/768 ,  H01L29/66 ,  H01L21/308 ,  H01L27/088 ,  H01L49/02 ,  H01L21/8234 ,  H01L27/06

Abstract: A semiconductor device including a metal pattern on a semiconductor substrate; an etch stop layer covering the metal pattern, the etch stop layer including a sequentially stacked first insulation layer, second insulation layer, and third insulation layer; an interlayer dielectric layer on the etch stop layer; and a contact plug penetrating the interlayer dielectric layer and the etch stop layer, the contact plug being connected to the metal pattern, wherein the first insulation layer includes a first insulating material that contains a metallic element and nitrogen, wherein the second insulation layer includes a second insulating material that contains carbon, and wherein the third insulation layer includes a third insulating material that does not contain a metallic element and carbon.

公开(公告)号：US20210217749A1

公开(公告)日：2021-07-15

申请号：US16888209

申请日：2020-05-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghyun LEE ,  Sungwoo KANG ,  Jongchul PARK ,  Youngmook OH ,  Jeongyun LEE

IPC: H01L27/088 ,  H01L21/768 ,  H01L29/417

Abstract: A semiconductor device according to some embodiments of the disclosure may include a fin type active pattern extending in a first direction, a plurality of gate structures on the fin type active pattern and extending in a second direction different from the first direction, a plurality of inter-contact insulation patterns on respective ones of the plurality of gate structures, a plurality of interlayer insulation layers on side surfaces of the plurality of gate structures, and a plurality of contact plugs respectively between pairs of the plurality of gate structures. The fin type active pattern may include a plurality of source/drains. Lower ends of the plurality of contact plugs may contact the plurality of source/drains. The plurality of gate structures may each include a first gate metal, a second gate metal, a gate capping layer, a gate insulation layer, a first spacer, and a second spacer.

公开(公告)号：US20180182845A1

公开(公告)日：2018-06-28

申请号：US15662248

申请日：2017-07-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： GeumJung SEONG ,  JeongYun LEE ,  SeungSoo HONG ,  KyungSeok MIN ,  SeungJu PARK ,  Youngmook OH ,  Bora LIM

IPC: H01L29/06 ,  H01L21/8234 ,  H01L21/764 ,  H01L27/088 ,  H01L29/08 ,  H01L23/535

CPC classification number: H01L29/0653 ,  H01L21/764 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/0847

Abstract: Active patterns protrude from a substrate. The active patterns include a first active pattern, a second active pattern spaced apart from the first active pattern at a first distance, and a third active pattern spaced apart from the second active pattern at a second distance greater than the first distance. A gate spacer is disposed on sidewalls of a gate electrode running across the active patterns. Source/drain regions include a first to a third source/drain regions disposed on a region of one of the active patterns. The region of one of the active patterns is disposed adjacent to a side of the gate electrode. First and second protective insulation patterns are disposed on the substrate between the first and second active patterns below the first and second source/drain regions and between the second and third active patterns below the second and third source/drain regions, respectively.