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公开(公告)号：US11437094B2
公开(公告)日：2022-09-06
申请号：US17018097
申请日：2020-09-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyejin Yim , Sung-Won Yun , Il Han Park
Abstract: A memory device includes: a first substrate; a peripheral circuit provided on the first substrate; a first metal bonding layer provided on the peripheral circuit; a second metal bonding layer directly bonded to the first metal bonding layer; a memory cell array provided on the second metal bonding layer; and a second substrate provided on the memory cell array. A page buffer circuit in the peripheral circuit receives a verification result through the metal bonding layers, divides the verification result into stages, and sequentially outputs the verification result for the division into the stages, and a pass/failure checker in the peripheral circuit sequentially performs a counting operation about each of the stages to generate accumulated values, and compares the accumulated values and a reference value which increases from an initial value as the counting operation is performed, and the initial value is set by an external memory controller.
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公开(公告)号：US10748632B2
公开(公告)日：2020-08-18
申请号：US16198013
申请日：2018-11-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sung-Won Yun , Hye-Jin Yim
Abstract: A nonvolatile memory device includes multiple memory cells including first memory cells and second memory cells. A method of programming the nonvolatile memory device includes: performing first programming to apply a programming forcing voltage to a bit line of each of the first memory cells; and dividing the second memory cells into a first cell group, a second cell group, and a third cell group, based on a threshold voltage of the second memory cells after performing the first programming. The method also includes performing second programming to apply a programming inhibition voltage to the bit line of each of the first memory cells and a bit line of each of memory cells of the first cell group. A level of the programming forcing voltage is lower than that of the programming inhibition voltage.
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公开(公告)号：US10061633B2
公开(公告)日：2018-08-28
申请号：US15155162
申请日：2016-05-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyejin Yim , Sung-Won Yun , Il Han Park
IPC: G06F11/07
CPC classification number: G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3459
Abstract: A program verification method for a nonvolatile memory device includes performing a first failure bit counting operation about a first stage to generate a first failure bit accumulated value and comparing the first failure bit accumulated value and a first failure reference value to determine a program failure. When the first failure bit accumulated value is less than the first failure reference value, a second failure bit counting operation for a second stage is performed to generate a second failure bit accumulated value. The second failure bit accumulated value is compared to a second reference value to determine a program failure. The second failure reference value is different from the first failure reference value.
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4.发明授权公开(公告)号：US09837164B2
公开(公告)日：2017-12-05
申请号：US15146911
申请日：2016-05-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sung-Won Yun
IPC: G11C11/34 , G11C16/34 , G11C16/26 , G11C16/04 , G11C16/24 , G11C11/56 , G11C16/10 , G11C16/14 , G11C16/30
CPC classification number: G11C16/3427 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/14 , G11C16/24 , G11C16/26 , G11C16/30 , G11C16/3418 , G11C16/3431
Abstract: A method is for operating a nonvolatile memory device, the nonvolatile memory device including at least one string connected to a bit line, the at least one string including a plurality of memory cells connected in series, each of the plurality of memory cells being connected to a respective word line among a plurality of word lines and stacked in a direction perpendicular to a substrate. The method includes applying a word line voltage needed for an operation to a first word line among the word lines, applying a recovery voltage higher than a ground voltage to the first word line after the operation, and then floating the first word line.
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公开(公告)号：US11776642B2
公开(公告)日：2023-10-03
申请号：US17548774
申请日：2021-12-13
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sung-Won Yun , Han-Jun Lee
CPC classification number: G11C16/349 , G11C11/5628 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/3404 , G11C16/3459 , G11C29/021 , G11C29/028 , G11C16/0483
Abstract: A method of operating a memory device that includes a plurality of stages each having a plurality of page buffers. The method including performing a verify operation of a first program loop from among a plurality of program loops, the verify operation of the first program loop including, performing a first off-cell counting operation on a first stage of the plurality of stages based on a first sampling rate to generate a first off-cell counting result; selectively changing the first sampling rate based on the first off-cell counting result to generate a changed first sampling rate; and performing a second off-cell counting operation on a second stage of the plurality of stages based on one of the first sampling rate and the changed first sampling rate to generate a second off-cell counting result.
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Patent Agency Ranking
公开(公告)号：US11756613B2
公开(公告)日：2023-09-12
申请号：US17901308
申请日：2022-09-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyejin Yim , Sung-Won Yun , Il Han Park
CPC classification number: G11C11/5628 , G06F11/0793 , G11C16/10 , G11C16/3459 , G11C16/0483
Abstract: A memory device includes: a first substrate; a peripheral circuit provided on the first substrate; a first metal bonding layer provided on the peripheral circuit; a second metal bonding layer directly bonded to the first metal bonding layer; a memory cell array provided on the second metal bonding layer; and a second substrate provided on the memory cell array. A page buffer circuit in the peripheral circuit receives a verification result through the metal bonding layers, divides the verification result into stages, and sequentially outputs the verification result for the division into the stages, and a pass/failure checker in the peripheral circuit sequentially performs a counting operation about each of the stages to generate accumulated values, and compares the accumulated values and a reference value which increases from an initial value as the counting operation is performed, and the initial value is set by an external memory controller.
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7.发明授权Nonvolatile memory device, storage device having the same, and operation and read methods thereof 有权非易失性存储装置，具有该存储装置的存储装置及其操作和读取方法公开(公告)号：US09349471B2
公开(公告)日：2016-05-24
申请号：US14670879
申请日：2015-03-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sung-Won Yun
CPC classification number: G11C16/3427 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/14 , G11C16/24 , G11C16/26 , G11C16/30 , G11C16/3418 , G11C16/3431
Abstract: A method is for operating a nonvolatile memory device, the nonvolatile memory device including at least one string connected to a bit line, the at least one string including a plurality of memory cells connected in series, each of the plurality of memory cells being connected to a respective word line among a plurality of word lines and stacked in a direction perpendicular to a substrate. The method includes applying a word line voltage needed for an operation to a first word line among the word lines, applying a recovery voltage higher than a ground voltage to the first word line after the operation, and then floating the first word line.
Abstract translation: 一种用于操作非易失性存储器件的方法，所述非易失性存储器件包括连接到位线的至少一个串，所述至少一个串包括串联连接的多个存储器单元，所述多个存储器单元中的每一个连接到 多个字线中的相应字线并且在垂直于衬底的方向上堆叠。 该方法包括将字线所需的字线电压应用于字线中的第一字线，在操作之后对第一字线施加高于接地电压的恢复电压，然后浮置第一字线。
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公开(公告)号：US10777264B2
公开(公告)日：2020-09-15
申请号：US16108408
申请日：2018-08-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyejin Yim , Sung-Won Yun , Il Han Park
Abstract: A program verification method for a nonvolatile memory device includes performing a first failure bit counting operation about a first stage to generate a first failure bit accumulated value and comparing the first failure bit accumulated value and a first failure reference value to determine a program failure. When the first failure bit accumulated value is less than the first failure reference value, a second failure bit counting operation for a second stage is performed to generate a second failure bit accumulated value. The second failure bit accumulated value is compared to a second reference value to determine a program failure. The second failure reference value is different from the first failure reference value.
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公开(公告)号：USRE46887E1
公开(公告)日：2018-06-05
申请号：US14805938
申请日：2015-07-22
Applicant: Samsung Electronics Co., Ltd.
Inventor： ChiWeon Yoon , Donghyuk Chae , Sang-Wan Nam , Sung-Won Yun
IPC: G11C11/34 , G11C16/04 , G11C16/10 , G11C16/34 , H01L29/792 , H01L27/11582 , H01L29/788 , H01L27/11556
CPC classification number: G11C16/10 , G11C16/0483 , G11C16/3418 , H01L27/11556 , H01L27/11582 , H01L29/7889 , H01L29/7926
Abstract: Non-volatile memory device channel boosting methods in which at least two strings are connected to one bit line, the channel boosting methods including applying an initial channel voltage to channels of strings in a selected memory block, floating inhibit strings each having an un-programmed cell among the strings, and boosting channels of the floated inhibit strings.
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公开(公告)号：US09899097B2
公开(公告)日：2018-02-20
申请号：US15381724
申请日：2016-12-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Youngmin Kim , Il Han Park , Sung-Won Yun , Hyejin Yim
CPC classification number: G11C16/3459 , G11C11/5671 , G11C16/08 , G11C16/10 , G11C16/3481 , G11C2211/562 , G11C2211/5621 , G11C2211/5644
Abstract: A nonvolatile memory device is provided as follows. A memory cell array includes a plurality of memory cells. An address decoder provides a first verify voltage to selected memory cells among the plurality of memory cells in a first program loop and provides a second verify voltage to the selected memory cells in a second program loop. A control logic determines the second program loop as a verify voltage offset point in which the first verify voltage is changed to the second verify voltage based on a result of a verify operation of the first program loop.
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