公开(公告)号：US10061633B2

公开(公告)日：2018-08-28

申请号：US15155162

申请日：2016-05-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyejin Yim ,  Sung-Won Yun ,  Il Han Park

IPC: G06F11/07

CPC classification number: G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3459

Abstract: A program verification method for a nonvolatile memory device includes performing a first failure bit counting operation about a first stage to generate a first failure bit accumulated value and comparing the first failure bit accumulated value and a first failure reference value to determine a program failure. When the first failure bit accumulated value is less than the first failure reference value, a second failure bit counting operation for a second stage is performed to generate a second failure bit accumulated value. The second failure bit accumulated value is compared to a second reference value to determine a program failure. The second failure reference value is different from the first failure reference value.

公开(公告)号：US11756613B2

公开(公告)日：2023-09-12

申请号：US17901308

申请日：2022-09-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyejin Yim ,  Sung-Won Yun ,  Il Han Park

IPC: G06F11/07 ,  G11C11/56 ,  G11C16/34 ,  G11C16/10 ,  G11C16/04

CPC classification number: G11C11/5628 ,  G06F11/0793 ,  G11C16/10 ,  G11C16/3459 ,  G11C16/0483

Abstract: A memory device includes: a first substrate; a peripheral circuit provided on the first substrate; a first metal bonding layer provided on the peripheral circuit; a second metal bonding layer directly bonded to the first metal bonding layer; a memory cell array provided on the second metal bonding layer; and a second substrate provided on the memory cell array. A page buffer circuit in the peripheral circuit receives a verification result through the metal bonding layers, divides the verification result into stages, and sequentially outputs the verification result for the division into the stages, and a pass/failure checker in the peripheral circuit sequentially performs a counting operation about each of the stages to generate accumulated values, and compares the accumulated values and a reference value which increases from an initial value as the counting operation is performed, and the initial value is set by an external memory controller.

公开(公告)号：US11437094B2

公开(公告)日：2022-09-06

申请号：US17018097

申请日：2020-09-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyejin Yim ,  Sung-Won Yun ,  Il Han Park

IPC: G06F11/07 ,  G11C11/56 ,  G11C16/34 ,  G11C16/10 ,  G11C16/04

Abstract: A memory device includes: a first substrate; a peripheral circuit provided on the first substrate; a first metal bonding layer provided on the peripheral circuit; a second metal bonding layer directly bonded to the first metal bonding layer; a memory cell array provided on the second metal bonding layer; and a second substrate provided on the memory cell array. A page buffer circuit in the peripheral circuit receives a verification result through the metal bonding layers, divides the verification result into stages, and sequentially outputs the verification result for the division into the stages, and a pass/failure checker in the peripheral circuit sequentially performs a counting operation about each of the stages to generate accumulated values, and compares the accumulated values and a reference value which increases from an initial value as the counting operation is performed, and the initial value is set by an external memory controller.

公开(公告)号：US10777264B2

公开(公告)日：2020-09-15

申请号：US16108408

申请日：2018-08-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyejin Yim ,  Sung-Won Yun ,  Il Han Park

IPC: G06F11/07 ,  G11C11/56 ,  G11C16/10 ,  G11C16/34 ,  G11C16/04

Abstract: A program verification method for a nonvolatile memory device includes performing a first failure bit counting operation about a first stage to generate a first failure bit accumulated value and comparing the first failure bit accumulated value and a first failure reference value to determine a program failure. When the first failure bit accumulated value is less than the first failure reference value, a second failure bit counting operation for a second stage is performed to generate a second failure bit accumulated value. The second failure bit accumulated value is compared to a second reference value to determine a program failure. The second failure reference value is different from the first failure reference value.

公开(公告)号：US09899097B2

公开(公告)日：2018-02-20

申请号：US15381724

申请日：2016-12-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngmin Kim ,  Il Han Park ,  Sung-Won Yun ,  Hyejin Yim

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/08 ,  G11C16/10

CPC classification number: G11C16/3459 ,  G11C11/5671 ,  G11C16/08 ,  G11C16/10 ,  G11C16/3481 ,  G11C2211/562 ,  G11C2211/5621 ,  G11C2211/5644

Abstract: A nonvolatile memory device is provided as follows. A memory cell array includes a plurality of memory cells. An address decoder provides a first verify voltage to selected memory cells among the plurality of memory cells in a first program loop and provides a second verify voltage to the selected memory cells in a second program loop. A control logic determines the second program loop as a verify voltage offset point in which the first verify voltage is changed to the second verify voltage based on a result of a verify operation of the first program loop.