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公开(公告)号:US20250006792A1
公开(公告)日:2025-01-02
申请号:US18411313
申请日:2024-01-12
Applicant: Samsung Electronics Co., Ltd.
Inventor: Tae Hyun Ryu , Dong Hoon Hwang , Myung Il Kang , Hyo Jin Kim , Byung Ho Moon , Nam Hyun Lee
IPC: H01L29/10 , H01L29/417
Abstract: A semiconductor device includes a first and second channel separation structures extending in a first direction and spaced apart from each other in a second direction, first gate structures spaced apart from each other in the first direction between the first and second channel separation structures and in contact with the first and second channel separation structures, first and second channel patterns including first and second sheet patterns, respectively, spaced apart from each other in a third direction and in contact with the corresponding first and second channel separation structures, first and second source/drain patterns between the first and second channel separation structures, the first source/drain patterns in contact with the first channel patterns and the first channel separation structure, the second source/drain patterns in contact with the second channel patterns and the second channel separation structure, and first gate separation structures between the first and second source/drain patterns.
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公开(公告)号:US11508751B2
公开(公告)日:2022-11-22
申请号:US17144458
申请日:2021-01-08
Applicant: Samsung Electronics Co., Ltd.
Inventor: Namkyu Edward Cho , Seok Hoon Kim , Myung Il Kang , Geo Myung Shin , Seung Hun Lee , Jeong Yun Lee , Min Hee Choi , Jeong Min Choi
IPC: H01L29/66 , H01L29/78 , H01L27/11582 , H01L21/768
Abstract: A semiconductor device includes an active fin on a substrate, a gate electrode and intersecting the active fin, gate spacer layers on both side walls of the gate electrode, and a source/drain region in a recess region of the active fin at at least one side of the gate electrode. The source/drain region may include a base layer in contact with the active fin, and having an inner end and an outer end opposing each other in the first direction on an inner sidewall of the recess region. The source/drain region may include a first layer on the base layer. The first layer may include germanium (Ge) having a concentration higher than a concentration of germanium (Ge) included in the base layer. The outer end of the base layer may contact the first layer, and may have a shape convex toward outside of the gate electrode on a plane.
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公开(公告)号:US10109717B2
公开(公告)日:2018-10-23
申请号:US15596152
申请日:2017-05-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jung Han Lee , Myung Il Kang , Jae Hwan Lee , Sun Wook Kim , Seong Ju Kim , Sung Jin Park , Hong Seon Yang , Joo Hee Jung
Abstract: A semiconductor device including a first fin protruding on a substrate and extending in a first direction; a first gate electrode on the first fin, the first gate electrode intersecting the first fin; a first trench formed within the first fin at a side of the first gate electrode; a first epitaxial layer filling a portion of the first trench, wherein a thickness of the first epitaxial layer becomes thinner closer to a sidewall of the first trench; and a second epitaxial layer filling the first trench on the first epitaxial layer, wherein a boron concentration of the second epitaxial layer is greater than a boron concentration of the first epitaxial layer.
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公开(公告)号:US10586852B2
公开(公告)日:2020-03-10
申请号:US16156062
申请日:2018-10-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jung Han Lee , Myung Il Kang , Jae Hwan Lee , Sun Wook Kim , Seong Ju Kim , Sung Jin Park , Hong Seon Yang , Joo Hee Jung
Abstract: A semiconductor device including a first fin protruding on a substrate and extending in a first direction; a first gate electrode on the first fin, the first gate electrode intersecting the first fin; a first trench formed within the first fin at a side of the first gate electrode; a first epitaxial layer filling a portion of the first trench, wherein a thickness of the first epitaxial layer becomes thinner closer to a sidewall of the first trench; and a second epitaxial layer filling the first trench on the first epitaxial layer, wherein a boron concentration of the second epitaxial layer is greater than a boron concentration of the first epitaxial layer.
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公开(公告)号:US09881838B2
公开(公告)日:2018-01-30
申请号:US15413472
申请日:2017-01-24
Applicant: Samsung Electronics Co., Ltd.
Inventor: Yoon Hae Kim , Jin Wook Lee , Jong Ki Jung , Myung Il Kang , Kwang Yong Yang , Kwan Heum Lee , Byeong Chan Lee
IPC: H01L21/82 , H01L21/8234 , H01L29/66 , H01L21/308 , H01L29/08 , H01L21/311 , H01L21/3105 , H01L29/78 , H01L27/088 , H01L29/165 , H01L27/11 , H01L21/8238 , H01L27/092
CPC classification number: H01L21/823431 , H01L21/308 , H01L21/31053 , H01L21/31111 , H01L21/31116 , H01L21/823418 , H01L21/823437 , H01L21/823468 , H01L21/823814 , H01L21/823821 , H01L21/823828 , H01L21/823864 , H01L27/0207 , H01L27/088 , H01L27/0886 , H01L27/092 , H01L27/0924 , H01L27/1104 , H01L29/0847 , H01L29/165 , H01L29/6653 , H01L29/66545 , H01L29/66636 , H01L29/7848
Abstract: A semiconductor device includes a substrate having a first region and a second region, a plurality of first gate structures in the first region, the first gate structures being spaced apart from each other by a first distance, a plurality of second gate structures in the second region, the second gate structures being spaced apart from each other by a second distance, a first spacer on sidewalls of the first gate structures, a dielectric layer on the first spacer, a second spacer on sidewalls of the second gate structures, and a third spacer on the second spacer.
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