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    Power supply circuit and related methods for generating a power supply voltage in a semiconductor package
    2.
    发明授权
    Power supply circuit and related methods for generating a power supply voltage in a semiconductor package 有权

    公开(公告)号：US10747246B2

    公开(公告)日：2020-08-18

    申请号：US16550513

    申请日：2019-08-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hee-Won Kang ,  In-Hyuk Go ,  Nam-Su Kim ,  Eun-Ji Moon ,  Jae-Sang Yun

    IPC: G05F1/46 ,  G05F1/565 ,  G11C5/14 ,  H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L25/18 ,  H01L23/31 ,  G11C16/30 ,  H01L23/498

    Abstract: A power supply circuit includes a first comparator, a second comparator, a first voltage regulator, an output terminal, a first path and a second path. The first comparator compares a first input voltage with a first reference voltage to generate a first control signal. The second comparator compares a second input voltage with the first reference voltage to generate a second control signal. A voltage level of the second input voltage is different from a voltage level of the first input voltage. The first voltage regulator is selectively enabled based on the first control signal and the second control signal, and generates a first voltage based on the first input voltage. A voltage level of the first voltage is substantially the same as the voltage level of the second input voltage. The output terminal is configured to output one of the second input voltage and the first voltage as a power supply voltage. The first path directly provides the first input voltage to the first voltage regulator. The second path directly provides the second input voltage to the output terminal. The second input voltage bypasses the first voltage.

    Electric device including branched signal lines, and electric device including printed circuit board
    3.
    发明授权
    Electric device including branched signal lines, and electric device including printed circuit board 有权

    公开(公告)号：US12229061B2

    公开(公告)日：2025-02-18

    申请号：US17670962

    申请日：2022-02-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kwangsoo Park ,  Jae-Sang Yun ,  Su-Jin Kim ,  Jiwoon Park

    IPC: G06F13/16 ,  G06F13/40

    Abstract: Disclosed is an electronic device which includes a plurality of memory devices, a memory controller, a first signal line that makes electrical connection between the memory controller and a first branch point, a second signal line that makes electrical connection between the first branch point and a second branch point, a third signal line that makes electrical connection between the first branch point and a third branch point, a fourth signal line that electrically connects the second branch point and the first memory device, a fifth signal line that electrically connects the second branch point and the second memory device, a sixth signal line that electrically connects the third branch point and the third memory device, and a stub that includes a first end electrically connected with at least one of the plurality of signal lines, and a second end being left open-circuit.

    Power supply circuit and related methods for generating a power supply voltage in a semiconductor package
    4.
    发明授权
    Power supply circuit and related methods for generating a power supply voltage in a semiconductor package 有权

    公开(公告)号：US10437272B2

    公开(公告)日：2019-10-08

    申请号：US15935114

    申请日：2018-03-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hee-Won Kang ,  In-Hyuk Go ,  Nam-Su Kim ,  Eun-Ji Moon ,  Jae-Sang Yun

    IPC: G05F1/46 ,  H01L25/065 ,  G11C5/14 ,  G05F1/565 ,  H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  G11C16/30 ,  H01L25/18

    Abstract: A power supply circuit includes a first comparator, a second comparator, a first voltage regulator, an output terminal, a first path and a second path. The first comparator compares a first input voltage with a first reference voltage to generate a first control signal. The second comparator compares a second input voltage with the first reference voltage to generate a second control signal. A voltage level of the second input voltage is different from a voltage level of the first input voltage. The first voltage regulator is selectively enabled based on the first control signal and the second control signal, and generates a first voltage based on the first input voltage. A voltage level of the first voltage is substantially the same as the voltage level of the second input voltage. The output terminal is configured to output one of the second input voltage and the first voltage as a power supply voltage. The first path directly provides the first input voltage to the first voltage regulator. The second path directly provides the second input voltage to the output terminal. The second input voltage bypasses the first voltage.

    STORAGE DEVICES HAVING MULTI DROP STRUCTURE
    5.
    发明公开
    STORAGE DEVICES HAVING MULTI DROP STRUCTURE 审中-公开

    公开(公告)号：US20240127869A1

    公开(公告)日：2024-04-18

    申请号：US18317344

    申请日：2023-05-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jae-Sang Yun ,  Kwang Soo Park ,  Ji Woon Park ,  Bong Gyu Kang ,  Su-Jin Kim

    IPC: G11C7/10 ,  G11C5/06 ,  G11C5/14

    CPC classification number: G11C7/1039 ,  G11C5/06 ,  G11C5/14

    Abstract: A storage device having a multi drop structure is provided. The storage device comprises a storage controller configured to output a data signal, a first non-volatile memory configured to receive the data signal, a first wiring electrically connected to the storage controller and configured to transfer the data signal, a first termination module including a first impedance element that electrically connects the first wiring to at least one of a power voltage or a ground voltage, a second wiring electrically connected to the first wiring and configured to transfer the data signal to the first non-volatile memory, and a third wiring electrically connected to the first wiring and configured to transfer the data signal to the first termination module.

    Solid state drive device and method for fabricating solid state drive device
    6.
    发明授权
    Solid state drive device and method for fabricating solid state drive device 有权

    公开(公告)号：US11881279B2

    公开(公告)日：2024-01-23

    申请号：US17879479

    申请日：2022-08-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ji Woon Park ,  Jae-Sang Yun

    IPC: G11C5/06 ,  H01L23/00 ,  G11C5/02

    CPC classification number: G11C5/06 ,  G11C5/025 ,  H01L24/45

    Abstract: A solid state drive (SSD) device, including a substrate; a first buffer chip disposed on the substrate; a second buffer chip disposed on the first buffer chip; a plurality of first nonvolatile memory chips connected to the second buffer chip through wire bonding; a controller configured to transmit a control signal to the plurality of first nonvolatile memory chips through a first channel; and a first redistribution layer disposed in the substrate and configured to electrically connect the first channel to the first buffer chip, wherein the first buffer chip is connected to the first redistribution layer through flip chip bonding, and the second buffer chip is connected to the first redistribution layer through a first wire.

    Solid state drive device and method for fabricating solid state drive device
    7.
    发明授权
    Solid state drive device and method for fabricating solid state drive device 有权

    公开(公告)号：US11423950B2

    公开(公告)日：2022-08-23

    申请号：US16885832

    申请日：2020-05-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ji Woon Park ,  Jae-Sang Yun

    IPC: G11C5/06 ,  G11C5/02 ,  H01L23/00

    Abstract: A solid state drive (SSD) device, including a substrate; a first buffer chip disposed on the substrate; a second buffer chip disposed on the first buffer chip; a plurality of first nonvolatile memory chips connected to the second buffer chip through wire bonding; a controller configured to transmit a control signal to the plurality of first nonvolatile memory chips through a first channel; and a first redistribution layer disposed in the substrate and configured to electrically connect the first channel to the first buffer chip, wherein the first buffer chip is connected to the first redistribution layer through flip chip bonding, and the second buffer chip is connected to the first redistribution layer through a first wire.

    SOLID STATE DRIVE DEVICE AND METHOD FOR FABRICATING SOLID STATE DRIVE DEVICE
    8.
    发明申请
    SOLID STATE DRIVE DEVICE AND METHOD FOR FABRICATING SOLID STATE DRIVE DEVICE 有权

    公开(公告)号：US20210090612A1

    公开(公告)日：2021-03-25

    申请号：US16885832

    申请日：2020-05-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ji Woon PARK ,  Jae-Sang Yun

    IPC: G11C5/06 ,  G11C5/02 ,  H01L23/00

    Abstract: A solid state drive (SSD) device, including a substrate; a first buffer chip disposed on the substrate; a second buffer chip disposed on the first buffer chip; a plurality of first nonvolatile memory chips connected to the second buffer chip through wire bonding; a controller configured to transmit a control signal to the plurality of first nonvolatile memory chips through a first channel; and a first redistribution layer disposed in the substrate and configured to electrically connect the first channel to the first buffer chip, wherein the first buffer chip is connected to the first redistribution layer through flip chip bonding, and the second buffer chip is connected to the first redistribution layer through a first wire.

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