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    SEMICONDUCTOR DEVICE AND AN ELECTRONIC SYSTEM INCLUDING THE SAME
    1.
    发明公开
    SEMICONDUCTOR DEVICE AND AN ELECTRONIC SYSTEM INCLUDING THE SAME 审中-公开

    公开(公告)号：US20240063113A1

    公开(公告)日：2024-02-22

    申请号：US18192031

    申请日：2023-03-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sanghun CHUN ,  HOYOUNG CHOI ,  Haeli PARK ,  JEEHOON HAN

    IPC: H01L23/522 ,  H10B43/27 ,  H10B41/27 ,  H10B80/00 ,  H01L21/768

    CPC classification number: H01L23/5226 ,  H10B43/27 ,  H10B41/27 ,  H10B80/00 ,  H01L21/76804 ,  H01L21/76829 ,  H10B41/10

    Abstract: A semiconductor device including: a first gate stack including first insulating patterns and first conductive patterns; a second gate stack on the first gate stack, the second gate stack including second insulating patterns and second conductive patterns; a memory channel structure penetrating the first and second gate stacks; a penetration contact penetrating the first and second gate stacks; and a barrier pattern on opposite sides of the penetration contact, the first insulating patterns include a first connection insulating pattern, which is an uppermost one of the first insulating patterns, the second insulating patterns include a second connection insulating pattern which is in contact with a top surface of the first connection insulating pattern, a bottom surface of the barrier pattern is in contact with the top surface of the first connection insulating pattern, and a top surface of the barrier pattern is in contact with the second connection insulating pattern.

    THREE-DIMENSIONAL (3D) SEMICONDUCTOR MEMORY DEVICE
    3.
    发明申请
    THREE-DIMENSIONAL (3D) SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20230076039A1

    公开(公告)日：2023-03-09

    申请号：US17983024

    申请日：2022-11-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： KWANGYOUNG JUNG ,  SANGYOUN JO ,  KOHJI KANAMORI ,  JEEHOON HAN

    IPC: H01L27/11573 ,  H01L27/11556 ,  H01L27/11582 ,  G11C7/18 ,  H01L27/11519 ,  G11C16/08 ,  H01L27/11534 ,  H01L27/11565

    Abstract: A 3D semiconductor memory device includes a peripheral circuit structure including a first row decoder region, a second row decoder region, and a control circuit region between the first and second row decoder regions, a first electrode structure and a second electrode structure on the peripheral circuit structure, spaced apart in a first direction, and each including stacked electrodes, a mold structure on the peripheral circuit structure between the first and second electrode structures and including stacked sacrificial layers, vertical channel structures penetrating the first and second electrode structures, a separation insulating pattern provided between the first electrode structure and the mold structure and penetrating the mold structure, and a separation structure intersecting the first electrode structure in the first direction and extending to the separation insulating pattern, wherein a maximum width of the separation insulating pattern in a second direction is greater than a maximum width of the separation structure in the second direction.

    SEMICONDUCTOR DEVICE AND AN ELECTRONIC SYSTEM INCLUDING THE SAME
    4.
    发明公开
    SEMICONDUCTOR DEVICE AND AN ELECTRONIC SYSTEM INCLUDING THE SAME 审中-公开

    公开(公告)号：US20240324231A1

    公开(公告)日：2024-09-26

    申请号：US18383532

    申请日：2023-10-25

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： JUSEONG MIN ,  JAE-BOK BAEK ,  JEEHOON HAN

    IPC: H10B43/40 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

    CPC classification number: H10B43/40 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

    Abstract: A semiconductor device includes: a gate electrode on a semiconductor substrate; a gate dielectric pattern between the gate electrode and the semiconductor substrate; a first semiconductor pattern on the semiconductor substrate adjacent to a first side of the gate electrode; and a second semiconductor pattern on the semiconductor substrate adjacent to a second side of the gate electrode, wherein the first semiconductor pattern includes: a first via part in contact with the semiconductor substrate; and a first plate part on the first via part, wherein the second semiconductor pattern includes: a second via part in contact with the semiconductor substrate; and a second plate part on the second via part, wherein each of the first and second plate parts extends lengthwise in a direction parallel to a top surface of the semiconductor substrate.

    VERTICAL MEMORY DEVICES
    8.
    发明公开
    VERTICAL MEMORY DEVICES 审中-公开

    公开(公告)号：US20230354594A1

    公开(公告)日：2023-11-02

    申请号：US18220073

    申请日：2023-07-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： DONGHWAN KIM ,  YOUNGHWAN SON ,  SHINHWAN KWAN ,  JEEHOON HAN

    IPC: H10B41/27 ,  H01L23/538 ,  G11C5/02 ,  H10B43/27

    CPC classification number: H10B41/27 ,  H01L23/5384 ,  G11C5/025 ,  H10B43/27

    Abstract: A vertical memory device includes gate electrodes, a channel, a first conductive through via, and insulation structures. The gate electrodes are spaced apart from each other on a substrate in a first direction substantially perpendicular to an upper surface of the substrate, and may be stacked in a staircase shape. The channel extends through the gate electrodes in the first direction. The first conductive through via extends through a conductive pad of a first gate electrode among the gate electrodes and is electrically connected thereto. The first conductive through via extends through second gate electrodes from among the gate electrodes that are under the first gate electrode. The insulation structures are formed between the first conductive through via and sidewalls of each of the second gate electrodes, and electrically insulates the first conductive through via from each of the second gate electrodes.

    THREE-DIMENSIONAL (3D) SEMICONDUCTOR MEMORY DEVICE
    9.
    发明申请
    THREE-DIMENSIONAL (3D) SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20210358935A1

    公开(公告)日：2021-11-18

    申请号：US17095821

    申请日：2020-11-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： KWANGYOUNG JUNG ,  SANGYOUN JO ,  KOHJI KANAMORI ,  JEEHOON HAN

    IPC: H01L27/11573 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11519 ,  G11C16/08 ,  H01L27/11534 ,  G11C7/18

    Abstract: A 3D semiconductor memory device includes a peripheral circuit structure including a first row decoder region, a second row decoder region, and a control circuit region between the first and second row decoder regions, a first electrode structure and a second electrode structure on the peripheral circuit structure, spaced apart in a first direction, and each including stacked electrodes, a mold structure on the peripheral circuit structure between the first and second electrode structures and including stacked sacrificial layers, vertical channel structures penetrating the first and second electrode structures, a separation insulating pattern provided between the first electrode structure and the mold structure and penetrating the mold structure, and a separation structure intersecting the first electrode structure in the first direction and extending to the separation insulating pattern, wherein a maximum width of the separation insulating pattern in a second direction is greater than a maximum width of the separation structure in the second direction.

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