公开(公告)号：US20200343350A1

公开(公告)日：2020-10-29

申请号：US16916643

申请日：2020-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heon Bok Lee ,  Chul Sung Kim ,  Sang Jin Hyun

IPC: H01L29/417 ,  H01L29/08 ,  B82Y10/00 ,  H01L29/786 ,  H01L29/66 ,  H01L29/775 ,  H01L21/285 ,  H01L21/768 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/78

Abstract: A gate all around field effect transistor (GAAFET) device may include a plurality of nanostructures that are spaced apart from one another in a channel region of the FET device above a substrate. A gate electrode can be in a GAA arrangement with the plurality of nanostructures and a semiconductor pattern can be on one side of the gate electrode. A contact in a contact trench in the semiconductor pattern and a silicide film can extend conformally on a side wall of the contact trench to a level in the channel region that is lower an uppermost one of the plurality of nanostructures.

公开(公告)号：US09859387B2

公开(公告)日：2018-01-02

申请号：US14990793

申请日：2016-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin Bum Kim ,  Chul Sung Kim ,  Kang Hun Moon ,  Yang Xu ,  Bon Young Koo

IPC: H01L27/088 ,  H01L29/417 ,  H01L29/78 ,  H01L29/08 ,  H01L29/161 ,  H01L29/36 ,  H01L29/45 ,  H01L29/66 ,  H01L27/11 ,  H01L29/775 ,  H01L29/06

CPC classification number: H01L29/41791 ,  H01L27/1104 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/36 ,  H01L29/41758 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: A semiconductor device includes a substrate having an upper surface, a plurality of active fins on the substrate, a gate electrode crossing the plurality of active fins, and at each side of the gate electrode, a source/drain region on the plurality of active fins. The source/drain region may include a plurality of first regions extending from the active fins, and a second region between each of the plurality of first regions. The second region may have a second germanium concentration greater than the first germanium concentration. The source/drain region may be connected to a contact plug, and may have a top surface that has a wave shaped, or curved surface. The top surface may have a larger surface area than a top surface of the contact plug.

公开(公告)号：US10998412B2

公开(公告)日：2021-05-04

申请号：US16916643

申请日：2020-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heon Bok Lee ,  Chul Sung Kim ,  Sang Jin Hyun

IPC: H01L29/417 ,  H01L29/08 ,  B82Y10/00 ,  H01L29/786 ,  H01L29/66 ,  H01L29/775 ,  H01L21/285 ,  H01L21/768 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/78 ,  H01L29/10

Abstract: A gate all around field effect transistor (GAAFET) device may include a plurality of nanostructures that are spaced apart from one another in a channel region of the FET device above a substrate. A gate electrode can be in a GAA arrangement with the plurality of nanostructures and a semiconductor pattern can be on one side of the gate electrode. A contact in a contact trench in the semiconductor pattern and a silicide film can extend conformally on a side wall of the contact trench to a level in the channel region that is lower an uppermost one of the plurality of nanostructures.

公开(公告)号：US10269629B2

公开(公告)日：2019-04-23

申请号：US15624783

申请日：2017-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghun Choi ,  Jeong Ik Kim ,  Myung Yang ,  Chul Sung Kim ,  Sang Jin Hyun

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/535 ,  H01L23/485 ,  H01L23/532

Abstract: A semiconductor device and a method of manufacturing the same, the semiconductor device including a substrate; an insulating layer on the substrate, the insulating layer including a first trench and a second trench therein, the second trench having an aspect ratio that is smaller than an aspect ratio of the first trench; a barrier layer in the first trench and the second trench; a seed layer on the barrier layer in the first trench and the second trench; a first bulk layer on the seed layer and filled in the first trench; and a second bulk layer on the seed layer and filled in the second trench, wherein an average grain size of the second bulk layer is larger than an average grain size of the first bulk layer.

公开(公告)号：US10714579B2

公开(公告)日：2020-07-14

申请号：US15999191

申请日：2018-08-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heon Bok Lee ,  Chul Sung Kim ,  Sang Jin Hyun

IPC: H01L29/417 ,  H01L29/08 ,  B82Y10/00 ,  H01L29/786 ,  H01L29/66 ,  H01L29/775 ,  H01L21/285 ,  H01L21/768 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/78 ,  H01L29/10

Abstract: A gate all around field effect transistor (GAAFET) device may include a plurality of nanostructures that are spaced apart from one another in a channel region of the FET device above a substrate. A gate electrode can be in a GAA arrangement with the plurality of nanostructures and a semiconductor pattern can be on one side of the gate electrode. A contact in a contact trench in the semiconductor pattern and a silicide film can extend conformally on a side wall of the contact trench to a level in the channel region that is lower an uppermost one of the plurality of nanostructures.

公开(公告)号：US10128245B2

公开(公告)日：2018-11-13

申请号：US15473031

申请日：2017-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Do Sun Lee ,  Joon Gon Lee ,  Na Rae Kim ,  Chul Sung Kim ,  Do Hyun Lee ,  Ryuji Tomita ,  Sang Jin Hyun

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/165 ,  H01L29/45 ,  H01L29/417 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/66 ,  H01L21/02 ,  H01L21/285

Abstract: Semiconductor devices may have a first semiconductor element including first active regions that are doped with a first conductivity-type impurity and that are on a semiconductor substrate, a first gate structure between the first active regions, and first contacts connected to the first active regions, respectively; and a second semiconductor element including second active regions that are doped with a second conductivity-type impurity different from the first conductivity-type impurity and that are on the semiconductor substrate, a second gate structure between the second active regions, and second contacts connected to the second active regions, respectively, and having a second length greater than a first length of each of the first contacts in a first direction parallel to an upper surface of the semiconductor substrate.

公开(公告)号：US20180090583A1

公开(公告)日：2018-03-29

申请号：US15473143

申请日：2017-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyo Seok Choi ,  Ryuji Tomita ,  Joon Gon Lee ,  Chul Sung Kim ,  Jae Eun Lee

IPC: H01L29/45 ,  H01L23/535 ,  H01L29/08 ,  H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L21/768 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/823821 ,  H01L21/845 ,  H01L23/485 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/41766 ,  H01L29/41791 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/785

Abstract: A semiconductor device includes a substrate including an active region, a gate structure, source/drain regions, ones of the source/drain regions having an upper surface in which a recessed region is formed, a contact plug on the source/drain regions and extending in a direction substantially perpendicular to an upper surface of the substrate from an interior of the recessed region, a metal silicide film on an internal surface of the recessed region and including a first portion between a bottom surface of the recessed region and a lower surface of the contact plug and a second portion between a side wall of the recessed region and a side surface of the contact plug, and a metal layer connected to an upper portion of the metal silicide film and on a side surface of a region of the contact plug.

公开(公告)号：US11063036B2

公开(公告)日：2021-07-13

申请号：US15683050

申请日：2017-08-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyo Seok Choi ,  Chul Sung Kim ,  Jae Eun Lee

IPC: H01L29/78 ,  H01L21/8234 ,  H01L23/485 ,  H01L27/06 ,  H01L49/02 ,  H01L29/775 ,  H01L27/088 ,  H01L29/66 ,  H01L29/06

Abstract: A semiconductor device includes a substrate, a first recess formed in the substrate, a first source/drain filling the first recess, a vertical metal resistor on the first source/drain, and an insulating liner separating the metal resistor from the first source/drain, with the vertical metal resistor being between two gate electrodes.

公开(公告)号：US10332984B2

公开(公告)日：2019-06-25

申请号：US15473143

申请日：2017-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyo Seok Choi ,  Ryuji Tomita ,  Joon Gon Lee ,  Chul Sung Kim ,  Jae Eun Lee

IPC: H01L29/78 ,  H01L29/66 ,  H01L23/535 ,  H01L29/417 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/40 ,  H01L21/84 ,  H01L27/12

Abstract: A semiconductor device includes a substrate including an active region, a gate structure, source/drain regions, ones of the source/drain regions having an upper surface in which a recessed region is formed, a contact plug on the source/drain regions and extending in a direction substantially perpendicular to an upper surface of the substrate from an interior of the recessed region, a metal silicide film on an internal surface of the recessed region and including a first portion between a bottom surface of the recessed region and a lower surface of the contact plug and a second portion between a side wall of the recessed region and a side surface of the contact plug, and a metal layer connected to an upper portion of the metal silicide film and on a side surface of a region of the contact plug.