公开(公告)号：US09659909B2

公开(公告)日：2017-05-23

申请号：US15013553

申请日：2016-02-02

Applicant: SK hynix Inc.

Inventor： Hee Min Shin ,  Mi Young Kim

IPC: H01L23/498 ,  H01L23/495 ,  H01L51/00 ,  H01L41/047 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L23/48 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49572 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5387 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L25/18 ,  H01L41/0475 ,  H01L51/0097 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/1441 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/85399

Abstract: A semiconductor package includes a first semiconductor package, a second semiconductor package disposed on the first semiconductor package, and a flexible wing interconnection substrate disposed between the first and second semiconductor packages.

公开(公告)号：US09305912B2

公开(公告)日：2016-04-05

申请号：US14734214

申请日：2015-06-09

Applicant: SK hynix Inc.

Inventor： Hee Min Shin ,  Cheol Ho Joh ,  Eun Hye Do ,  Ji Eun Kim ,  Kyu Won Lee

IPC: H01L25/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L21/78 ,  H01L25/11 ,  H01L23/538

CPC classification number: H01L25/50 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/5389 ,  H01L24/18 ,  H01L24/19 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/117 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2924/00

Abstract: A stack package includes a cover film, a first package having a first semiconductor chip which is attached to the cover film, a first adhesive member which is formed to seal the first semiconductor chip and a surface of the cover film, and a first circuit pattern which is disposed over the first adhesive member and electrically connected with the first semiconductor chip; a second package disposed over the first package, having a second semiconductor chip which is electrically connected with the first circuit pattern, a second adhesive member which is formed to seal the second semiconductor chip, and a second circuit pattern which is formed over the second adhesive member, and a via formed to pass through the second circuit pattern and the second adhesive member and to be electrically connected with the first circuit pattern and the second circuit pattern.

公开(公告)号：US09842809B2

公开(公告)日：2017-12-12

申请号：US14989246

申请日：2016-01-06

Applicant: SK hynix Inc.

Inventor： Ki Ill Moon ,  Myeong Seob Kim ,  Hee Min Shin

IPC: H01L23/552 ,  H01L23/498 ,  H01L23/544 ,  H01L23/29 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/552 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/544 ,  H01L24/06 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06135 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/3025 ,  H01L2224/45099

Abstract: A semiconductor package may include a semiconductor device mounted on a package substrate, a conductive roof located over the semiconductor device, a plurality of conductive walls disposed on the package substrate and arrayed in a closed loop line surrounding the semiconductor device. Conductive pillars may be disposed in regions between the conductive walls on the package substrate and bonded to the conductive roof. The semiconductor package may include a first dielectric layer filling a space between the package substrate and the conductive roof.

公开(公告)号：US09093441B2

公开(公告)日：2015-07-28

申请号：US13846713

申请日：2013-03-18

Applicant: SK hynix Inc.

Inventor： Ji Eun Kim ,  Cheol Ho Joh ,  Hee Min Shin ,  Kyu Won Lee ,  Chong Ho Cho

IPC: H01L25/04 ,  H01L25/065 ,  H01L25/075 ,  H01L23/498 ,  H01L21/683 ,  H01L25/00 ,  H01L29/06 ,  H01L23/00

CPC classification number: H01L23/49827 ,  H01L21/6836 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/78 ,  H01L24/92 ,  H01L25/043 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/0756 ,  H01L25/50 ,  H01L29/0657 ,  H01L2221/68327 ,  H01L2224/04042 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/49174 ,  H01L2224/73265 ,  H01L2224/78346 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10158 ,  H01L2924/1531 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The semiconductor package includes an upper semiconductor chip stacked on a package substrate and a support layer or a lower semiconductor chip disposed between the upper semiconductor chip and the package substrate. The upper semiconductor chip includes a protrusion downwardly extending from an edge thereof. The protrusion of the upper semiconductor chip is combined with a sidewall of the support layer or the lower semiconductor chip. Related methods are also provided.

Abstract translation: 半导体封装包括堆叠在封装衬底上的上半导体芯片和设置在上半导体芯片和封装衬底之间的支撑层或下半导体芯片。 上半导体芯片包括从其边缘向下延伸的突起。 上半导体芯片的突起与支撑层或下半导体芯片的侧壁组合。 还提供了相关方法。

公开(公告)号：US08951810B2

公开(公告)日：2015-02-10

申请号：US13719082

申请日：2012-12-18

Applicant: SK hynix Inc.

Inventor： Kyu Won Lee ,  Cheol Ho Joh ,  Ji Eun Kim ,  Hee Min Shin ,  Chong Ho Cho

IPC: H01L21/00 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L21/4846 ,  H01L21/4867 ,  H01L23/3178 ,  H01L23/49838 ,  H01L23/49866 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/02311 ,  H01L2224/02317 ,  H01L2224/02375 ,  H01L2224/0332 ,  H01L2224/03515 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05554 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Methods of forming an interconnection line pattern using a screen printing technique. The method includes preparing a substrate having unevenness, aligning a stencil mask on the substrate, and printing a paste including materials for forming the interconnection line pattern on a convex portion of the unevenness formed on the substrate.

Abstract translation: 使用丝网印刷技术形成互连线图案的方法。 该方法包括制备具有凹凸的基板，使基板上的模板掩模对准，以及在形成在基板上的凹凸的凸部上印刷包括用于形成互连线图案的材料的浆料。