公开(公告)号：US09165899B2

公开(公告)日：2015-10-20

申请号：US14083687

申请日：2013-11-19

Applicant: SK hynix Inc.

Inventor： Cheol Ho Joh

IPC: H01L23/488 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L24/14 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2924/00

Abstract: The disclosure relates to a stacked package and a method for manufacturing the same. The stacked package includes: a lower package including a substrate formed with ball lands in a periphery of an upper surface thereof, a semiconductor chip mounted over the upper surface, first solder balls formed over the ball lands and each having a side surface cut along an edge of the substrate and a polished upper surface, and a mold part for molding the upper surface including the semiconductor chip and the first solder balls, the cutted side surfaces and polished upper surfaces being exposed by the mold part; and an upper package stacked over the lower package and provided with second solder balls bonded to the first solder balls.

Abstract translation: 本发明涉及堆叠式封装及其制造方法。 堆叠式封装包括：下部封装，其包括在其上表面的周边形成有球形焊盘的基板，安装在上表面上的半导体芯片，形成在球台上的第一焊球，并且每个具有侧表面沿着 基板的边缘和抛光的上表面，以及用于模制包括半导体芯片和第一焊球的上表面的模具部分，被切割的侧表面和抛光的上表面被模具部分露出; 以及堆叠在下封装上的上封装，并且设置有与第一焊球接合的第二焊球。

公开(公告)号：US09093441B2

公开(公告)日：2015-07-28

申请号：US13846713

申请日：2013-03-18

Applicant: SK hynix Inc.

Inventor： Ji Eun Kim ,  Cheol Ho Joh ,  Hee Min Shin ,  Kyu Won Lee ,  Chong Ho Cho

IPC: H01L25/04 ,  H01L25/065 ,  H01L25/075 ,  H01L23/498 ,  H01L21/683 ,  H01L25/00 ,  H01L29/06 ,  H01L23/00

CPC classification number: H01L23/49827 ,  H01L21/6836 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/78 ,  H01L24/92 ,  H01L25/043 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/0756 ,  H01L25/50 ,  H01L29/0657 ,  H01L2221/68327 ,  H01L2224/04042 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/49174 ,  H01L2224/73265 ,  H01L2224/78346 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10158 ,  H01L2924/1531 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The semiconductor package includes an upper semiconductor chip stacked on a package substrate and a support layer or a lower semiconductor chip disposed between the upper semiconductor chip and the package substrate. The upper semiconductor chip includes a protrusion downwardly extending from an edge thereof. The protrusion of the upper semiconductor chip is combined with a sidewall of the support layer or the lower semiconductor chip. Related methods are also provided.

Abstract translation: 半导体封装包括堆叠在封装衬底上的上半导体芯片和设置在上半导体芯片和封装衬底之间的支撑层或下半导体芯片。 上半导体芯片包括从其边缘向下延伸的突起。 上半导体芯片的突起与支撑层或下半导体芯片的侧壁组合。 还提供了相关方法。

公开(公告)号：US08951810B2

公开(公告)日：2015-02-10

申请号：US13719082

申请日：2012-12-18

Applicant: SK hynix Inc.

Inventor： Kyu Won Lee ,  Cheol Ho Joh ,  Ji Eun Kim ,  Hee Min Shin ,  Chong Ho Cho

IPC: H01L21/00 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L21/4846 ,  H01L21/4867 ,  H01L23/3178 ,  H01L23/49838 ,  H01L23/49866 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/02311 ,  H01L2224/02317 ,  H01L2224/02375 ,  H01L2224/0332 ,  H01L2224/03515 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05554 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Methods of forming an interconnection line pattern using a screen printing technique. The method includes preparing a substrate having unevenness, aligning a stencil mask on the substrate, and printing a paste including materials for forming the interconnection line pattern on a convex portion of the unevenness formed on the substrate.

Abstract translation: 使用丝网印刷技术形成互连线图案的方法。 该方法包括制备具有凹凸的基板，使基板上的模板掩模对准，以及在形成在基板上的凹凸的凸部上印刷包括用于形成互连线图案的材料的浆料。

公开(公告)号：US09490187B2

公开(公告)日：2016-11-08

申请号：US14461126

申请日：2014-08-15

Applicant: SK hynix Inc.

Inventor： Cheol Ho Joh

IPC: H01L23/31 ,  H01L23/13 ,  H01L23/16 ,  H01L23/433 ,  H01L23/498

CPC classification number: H01L23/3157 ,  H01L23/13 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/48091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: The semiconductor package includes: a substrate having a window and first and second bond fingers arranged over a first surface along a periphery of the window; a first semiconductor chip disposed within the window and having a plurality of first bonding pads arranged over edges of an upper surface; a plurality of first connection members electrically coupling the first bonding pads with the first bonding fingers; a second semiconductor chip disposed over the first semiconductor chip and the first surface of the substrate and a plurality of second bonding pads in the edges of the lower surface; a plurality of second connection members electrically coupling the second bonding pads with the second bonding fingers of the substrate adjacent to the second bonding pads; and an encapsulation member formed over the first surface of the substrate to cover side surfaces of the second semiconductor chip.

Abstract translation: 所述半导体封装包括：具有窗口的基板和沿着所述窗口的周边布置在第一表面上的第一和第二接合指状物; 第一半导体芯片，设置在所述窗口内并且具有布置在上表面的边缘上的多个第一接合焊盘; 多个第一连接构件，其将所述第一接合焊盘与所述第一接合指状物电耦合; 设置在所述第一半导体芯片和所述基板的第一表面上的第二半导体芯片和在所述下表面的边缘中的多个第二焊盘; 多个第二连接构件将所述第二接合焊盘与所述衬底的与所述第二接合焊盘相邻的所述第二接合指电性地耦合; 以及形成在所述基板的所述第一表面上以覆盖所述第二半导体芯片的侧表面的封装构件。

公开(公告)号：US09305912B2

公开(公告)日：2016-04-05

申请号：US14734214

申请日：2015-06-09

Applicant: SK hynix Inc.

Inventor： Hee Min Shin ,  Cheol Ho Joh ,  Eun Hye Do ,  Ji Eun Kim ,  Kyu Won Lee

IPC: H01L25/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L21/78 ,  H01L25/11 ,  H01L23/538

CPC classification number: H01L25/50 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/5389 ,  H01L24/18 ,  H01L24/19 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/117 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2924/00

Abstract: A stack package includes a cover film, a first package having a first semiconductor chip which is attached to the cover film, a first adhesive member which is formed to seal the first semiconductor chip and a surface of the cover film, and a first circuit pattern which is disposed over the first adhesive member and electrically connected with the first semiconductor chip; a second package disposed over the first package, having a second semiconductor chip which is electrically connected with the first circuit pattern, a second adhesive member which is formed to seal the second semiconductor chip, and a second circuit pattern which is formed over the second adhesive member, and a via formed to pass through the second circuit pattern and the second adhesive member and to be electrically connected with the first circuit pattern and the second circuit pattern.

公开(公告)号：US08822271B2

公开(公告)日：2014-09-02

申请号：US13846640

申请日：2013-03-18

Applicant: SK hynix Inc.

Inventor： Cheol Ho Joh

IPC: H01L21/00 ,  H01L23/02 ,  H01L21/50

CPC classification number: H01L24/85 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/78 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05553 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/787 ,  H01L2224/78745 ,  H01L2224/789 ,  H01L2224/83191 ,  H01L2224/85181 ,  H01L2224/85186 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/10161 ,  Y10T29/53178 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2224/4554

Abstract: There are proposed a method and apparatus for manufacturing a chip package in which bonding wires are coupled with contact pads in which an overhang holder holds and fixes portions of a surface adjacent to portions where the contact pads are located.

Abstract translation: 提出了一种用于制造芯片封装的方法和装置，其中，接合线与接触焊盘耦合，其中突出支架保持并固定与接触垫所在部分相邻的表面的部分。