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    Semiconductor memory device with improved operation speed
    1.
    发明授权
    Semiconductor memory device with improved operation speed 有权

    公开(公告)号：US11342350B2

    公开(公告)日：2022-05-24

    申请号：US16700857

    申请日：2019-12-02

    申请人： SK hynix Inc.

    发明人： Sang Heon Lee ,  Hyun Heo

    IPC分类号： G11C5/06 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565

    摘要： A semiconductor memory device is provided. The semiconductor memory device includes a memory cell array disposed on a substrate, a bit line connected to the memory cell array, a peripheral circuit disposed between the memory cell array and the substrate, the peripheral circuit including a transistor, a conductive line disposed between the memory cell array and the transistor, a lower connection structure connecting the conductive line and the transistor, and two or more upper connection structures connecting the bit line and the conductive line, the two or more upper connection structures being spaced apart from each other.

    Semiconductor memory device
    2.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US09030901B2

    公开(公告)日：2015-05-12

    申请号：US13716047

    申请日：2012-12-14

    申请人： SK Hynix Inc.

    发明人： Hyun Heo

    IPC分类号： G11C7/00 ,  G11C7/12 ,  G11C8/00 ,  G11C8/12 ,  G11C16/12

    CPC分类号： G11C7/12 ,  G11C8/00 ,  G11C8/12 ,  G11C16/12

    摘要： A semiconductor memory device includes a first memory block group including memory blocks coupled to first sub bit lines, a second memory block group including memory blocks coupled to second sub bit lines, an operation circuit coupled to main bit lines, and configured to perform an operation for data input/output to/from a memory block selected from the first memory block group or the second memory block group, and a bit line control circuit configured to differently control sub bit lines of the selected memory block group and sub bit lines of the unselected memory block groups in response to group select signals for selecting a memory block group including the selected memory block of the first memory block group and the second memory block group and voltages of the main bit lines controlled by the operation circuit.

    摘要翻译： 一种半导体存储器件包括：第一存储块组，包括耦合到第一子位线的存储器块;第二存储块组，包括耦合到第二子位线的存储器块;耦合到主位线的操作电路，并且被配置为执行操作 用于对从第一存储块组或第二存储块组中选择的存储块的数据输入/输出进行数据输入/输出;以及位线控制电路，配置为不同地控制所选择的存储块组的子位线和 响应于用于选择包括所选择的第一存储器块组和第二存储器块组的存储块的存储器块组的组选择信号以及由操作电路控制的主位线的电压的未选择的存储块组。

    Semiconductor apparatus having transfer circuit transferring high voltage
    6.
    发明授权
    Semiconductor apparatus having transfer circuit transferring high voltage 有权
    具有传送电路的高电压的半导体装置

    公开(公告)号：US09467050B2

    公开(公告)日：2016-10-11

    申请号：US14477593

    申请日：2014-09-04

    申请人： SK hynix Inc.

    发明人： Yeonghun Lee ,  Hyun Heo ,  Min Gyu Koo ,  Dong Hwan Lee

    IPC分类号： H02M3/158 ,  G11C16/30 ,  G11C16/08 ,  G11C16/04

    CPC分类号： H02M3/158 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/30

    摘要： A semiconductor apparatus includes a voltage supply circuit suitable for outputting a high voltage, a transfer circuit coupled between the voltage supply circuit and a peripheral circuit and suitable for transferring the high voltage to the peripheral circuit and a transfer control circuit suitable for outputting a transfer control signal to the transfer circuit to control the transfer of the high voltage to the peripheral circuit, wherein the transfer control circuit outputs the transfer control signal having a first positive voltage level to a gate of a transistor included in the transfer circuit when the voltage supply circuit outputs the high voltage to the transfer circuit.

    摘要翻译： 半导体装置包括适于输出高电压的电压供给电路，耦合在电压供给电路和外围电路之间并适于将高电压传送到外围电路的转移电路，以及适于输出转移控制的转移控制电路 信号传送到传送电路以控制高电压传送到外围电路，其中传输控制电路在电压供应电路输出具有第一正电压电平的传输控制信号到包括在传送电路中的晶体管的栅极 将高电压输出到传输电路。

    3-dimensional semiconductor device having memory cells stacked over substrate
    7.
    发明授权
    3-dimensional semiconductor device having memory cells stacked over substrate 有权
    具有堆叠在基板上的存储单元的三维半导体器件

    公开(公告)号：US09299447B2

    公开(公告)日：2016-03-29

    申请号：US14490484

    申请日：2014-09-18

    申请人： SK hynix Inc.

    发明人： Yeonghun Lee ,  Hyun Heo ,  Min Gyu Koo ,  Dong Hwan Lee

    IPC分类号： G11C16/04 ,  G11C16/14 ,  G11C16/28

    CPC分类号： G11C16/14 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/28

    摘要： A semiconductor device includes a plurality of memory blocks, wherein each of the plurality of memory blocks includes a first select transistor electrically coupled to a common source line, a second select transistor electrically coupled to a bit line, and a plurality of memory cells electrically coupled between the first and second select transistors, and an operation circuit suitable for applying operation voltages for a program operation, a read operation, and an erase operation to a selected memory block selected from the plurality of memory blocks, and applying a first positive voltage to gates of the first select transistors in unselected memory blocks of the plurality of memory blocks when an erase voltage is applied to the common source line during the erase operation.

    摘要翻译： 半导体器件包括多个存储器块，其中多个存储器块中的每一个包括电耦合到公共源极线的第一选择晶体管，电耦合到位线的第二选择晶体管和电耦合的多个存储器单元 第一和第二选择晶体管之间的操作电压，以及适用于对从多个存储块中选择的所选择的存储块施加用于编程操作，读取操作和擦除操作的操作电压的操作电路，并且将第一正电压施加到 在擦除操作期间当向公共源极线施加擦除电压时，多个存储器块的未选择存储块中的第一选择晶体管的栅极。

    SEMICONDUCTOR MEMORY DEVICE
    9.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权
    半导体存储器件

    公开(公告)号：US20140064001A1

    公开(公告)日：2014-03-06

    申请号：US13716047

    申请日：2012-12-14

    申请人： SK HYNIX INC.

    发明人： Hyun Heo

    IPC分类号： G11C7/12 ,  G11C8/00

    CPC分类号： G11C7/12 ,  G11C8/00 ,  G11C8/12 ,  G11C16/12

    摘要： A semiconductor memory device includes a first memory block group including memory blocks coupled to first sub bit lines, a second memory block group including memory blocks coupled to second sub bit lines, an operation circuit coupled to main bit lines, and configured to perform an operation for data input/output to/from a memory block selected from the first memory block group or the second memory block group, and a bit line control circuit configured to differently control sub bit lines of the selected memory block group and sub bit lines of the unselected memory block groups in response to group select signals for selecting a memory block group including the selected memory block of the first memory block group and the second memory block group and voltages of the main bit lines controlled by the operation circuit.

    摘要翻译： 一种半导体存储器件包括：第一存储块组，包括耦合到第一子位线的存储器块;第二存储块组，包括耦合到第二子位线的存储器块;耦合到主位线的操作电路，并且被配置为执行操作 用于对从第一存储块组或第二存储块组中选择的存储块的数据输入/输出进行数据输入/输出;以及位线控制电路，配置为不同地控制所选择的存储块组的子位线和 响应于用于选择包括所选择的第一存储器块组和第二存储器块组的存储块的存储器块组的组选择信号以及由操作电路控制的主位线的电压的未选择的存储块组。