公开(公告)号：US20170047293A1

公开(公告)日：2017-02-16

申请号：US14989246

申请日：2016-01-06

Applicant: SK hynix Inc.

Inventor： Ki Ill MOON ,  Myeong Seob KIM ,  Hee Min SHIN

IPC: H01L23/552 ,  H01L23/498 ,  H01L23/58 ,  H01L23/31 ,  H01L23/29

CPC classification number: H01L23/552 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/544 ,  H01L24/06 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06135 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/3025 ,  H01L2224/45099

Abstract: A semiconductor package may include a semiconductor device mounted on a package substrate, a conductive roof located over the semiconductor device, a plurality of conductive walls disposed on the package substrate and arrayed in a closed loop line surrounding the semiconductor device. Conductive pillars may be disposed in regions between the conductive walls on the package substrate and bonded to the conductive roof. The semiconductor package may include a first dielectric layer filling a space between the package substrate and the conductive roof.

Abstract translation: 半导体封装可以包括安装在封装衬底上的半导体器件，位于半导体器件上方的导电屋顶，设置在封装衬底上并排列在围绕半导体器件的闭环线中的多个导电壁。 导电柱可以设置在封装衬底上的导电壁之间的区域中并且结合到导电屋顶。 半导体封装可以包括填充封装衬底和导电屋顶之间的空间的第一介电层。

公开(公告)号：US20170084579A1

公开(公告)日：2017-03-23

申请号：US15013553

申请日：2016-02-02

Applicant: SK hynix Inc.

Inventor： Hee Min SHIN ,  Mi Young KIM

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L23/31 ,  H01L23/538 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49572 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5387 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L25/18 ,  H01L41/0475 ,  H01L51/0097 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/1441 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/85399

Abstract: A semiconductor package includes a first semiconductor package, a second semiconductor package disposed on the first semiconductor package, and a flexible wing interconnection substrate disposed between the first and second semiconductor packages.

公开(公告)号：US20140175638A1

公开(公告)日：2014-06-26

申请号：US13846713

申请日：2013-03-18

Applicant: SK HYNIX INC.

Inventor： Ji Eun KIM ,  Cheol Ho JOH ,  Hee Min SHIN ,  Kyu Won LEE ,  Chong Ho CHO

IPC: H01L23/498

CPC classification number: H01L23/49827 ,  H01L21/6836 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/78 ,  H01L24/92 ,  H01L25/043 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/0756 ,  H01L25/50 ,  H01L29/0657 ,  H01L2221/68327 ,  H01L2224/04042 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/49174 ,  H01L2224/73265 ,  H01L2224/78346 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10158 ,  H01L2924/1531 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The semiconductor package includes an upper semiconductor chip stacked on a package substrate and a support layer or a lower semiconductor chip disposed between the upper semiconductor chip and the package substrate. The upper semiconductor chip includes a protrusion downwardly extending from an edge thereof. The protrusion of the upper semiconductor chip is combined with a sidewall of the support layer or the lower semiconductor chip. Related methods are also provided.

Abstract translation: 半导体封装包括堆叠在封装衬底上的上半导体芯片和设置在上半导体芯片和封装衬底之间的支撑层或下半导体芯片。 上半导体芯片包括从其边缘向下延伸的突起。 上半导体芯片的突起与支撑层或下半导体芯片的侧壁组合。 还提供了相关方法。

公开(公告)号：US20150270252A1

公开(公告)日：2015-09-24

申请号：US14734214

申请日：2015-06-09

Applicant: SK hynix Inc.

Inventor： Hee Min SHIN ,  Cheol Ho JOH ,  Eun Hye DO ,  Ji Eun KIM ,  Kyu Won LEE

IPC: H01L25/00 ,  H01L21/78 ,  H01L25/11

CPC classification number: H01L25/50 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/5389 ,  H01L24/18 ,  H01L24/19 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/117 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2924/00

Abstract: A stack package includes a cover film, a first package having a first semiconductor chip which is attached to the cover film, a first adhesive member which is formed to seal the first semiconductor chip and a surface of the cover film, and a first circuit pattern which is disposed over the first adhesive member and electrically connected with the first semiconductor chip; a second package disposed over the first package, having a second semiconductor chip which is electrically connected with the first circuit pattern, a second adhesive member which is formed to seal the second semiconductor chip, and a second circuit pattern which is formed over the second adhesive member, and a via formed to pass through the second circuit pattern and the second adhesive member and to be electrically connected with the first circuit pattern and the second circuit pattern.

Abstract translation: 叠层封装包括覆盖膜，具有附接到覆盖膜的第一半导体芯片的第一封装，形成为密封第一半导体芯片的第一粘合构件和覆盖膜的表面，以及第一电路图案 其设置在第一粘合构件上并与第一半导体芯片电连接; 第二封装，设置在所述第一封装上，具有与所述第一电路图案电连接的第二半导体芯片，形成为密封所述第二半导体芯片的第二粘合构件，以及形成在所述第二粘合剂上的第二电路图案 以及形成为穿过第二电路图案和第二粘合构件并且与第一电路图案和第二电路图案电连接的通孔。

公开(公告)号：US20130256887A1

公开(公告)日：2013-10-03

申请号：US13905254

申请日：2013-05-30

Applicant: SK hynix Inc.

Inventor： Kyu Won LEE ,  Cheol Ho JOH ,  Eun-Hye DO ,  Ji Eun KIM ,  Hee Min SHIN

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L21/561 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/03 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1064 ,  H01L2225/1076 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A stacked semiconductor package includes a semiconductor package module including a plurality of semiconductor packages each of which has a first surface, a second surface facing away from the first surface, side surfaces connecting the first surface and the second surface and through-holes formed on the side surfaces to pass through the first surface and the second surface and which are stacked such that their through-holes vertically connect with one another, and adhesive members which are formed between the semiconductor packages and attach the semiconductor packages to one another, a main substrate supporting the semiconductor package module and formed, on a third surface thereof facing the semiconductor package module, with main connection pads which are aligned with the through-holes, and conductive connection members formed in the through-holes and electrically connecting the semiconductor packages with the main connection pads.

Abstract translation: 堆叠半导体封装包括半导体封装模块，其包括多个半导体封装，每个半导体封装具有第一表面，背离第一表面的第二表面，连接第一表面和第二表面的侧表面和形成在第一表面上的通孔 侧表面通过第一表面和第二表面并且堆叠成使得它们的通孔彼此垂直连接;以及粘合构件，其形成在半导体封装之间并将半导体封装彼此附接，主基板 支撑半导体封装模块，并在其面向半导体封装模块的第三表面上形成与通孔对准的主连接焊盘，以及形成在通孔中的导电连接构件，并将半导体封装与 主连接垫