公开(公告)号：US20230253371A1

公开(公告)日：2023-08-10

申请号：US18304106

申请日：2023-04-20

Applicant: SK hynix Inc.

Inventor： Eun Hye DO ,  Jong Hoon KIM

IPC: H01L25/065

CPC classification number: H01L25/0657 ,  H01L2225/06506 ,  H01L2225/06586 ,  H01L2225/06562 ,  H01L2225/0651

Abstract: A semiconductor package includes: semiconductor chips being offset-stacked to expose edge regions adjacent to first side surfaces; chip pads disposed in each of the edge regions of the semiconductor chips, the chip pads including a plurality of first chip pads arranged in a first column and a plurality of second chip pads arranged in a second column; a horizontal common interconnector having one end connected to the second chip pad of a semiconductor chip of the semiconductor chips, and another end connected to the first chip pad of another semiconductor chip; and a vertical common interconnector having one end connected to the second chip pad of the uppermost semiconductor chip, which is electrically connected to the first chip pad of the uppermost semiconductor chip connected to the horizontal common interconnector.

公开(公告)号：US20240258201A1

公开(公告)日：2024-08-01

申请号：US18335868

申请日：2023-06-15

Applicant: SK hynix Inc.

Inventor： Eun Hye DO ,  Jong Hoon KIM

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/1146 ,  H01L2224/13147 ,  H01L2224/16145

Abstract: A semiconductor device is provided with differently-shaped conductive through-vias, having different-shape horizontal cross-sections. The cross-sectional shapes of the via include but are not limited to circular and ring shaped, which are cross sections that correspond to vias that are pillar shaped and tube-shaped respectively.

公开(公告)号：US20240339436A1

公开(公告)日：2024-10-10

申请号：US18483298

申请日：2023-10-09

Applicant: SK hynix Inc.

Inventor： Eun Hye DO ,  Chang Shik JUNG

IPC: H01L25/065 ,  H01L23/00 ,  H10B80/00

CPC classification number: H01L25/0657 ,  H01L24/48 ,  H10B80/00 ,  H01L24/32 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48105 ,  H01L2224/48149 ,  H01L2224/48227 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/1434

Abstract: A stack package is provided. The stack package includes a package substrate on which a first bond finger and a second bond finger are spaced apart from each other, and a second semiconductor die stacked over a first semiconductor die. A first connector connects the first semiconductor die to the first bond finger. A second connector connects the second semiconductor die to the second bond finger and extends to have substantially the same length as the first connector.

公开(公告)号：US20200091112A1

公开(公告)日：2020-03-19

申请号：US16230491

申请日：2018-12-21

Applicant: SK hynix Inc.

Inventor： Eun Hye DO

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31

Abstract: A stack package includes a second semiconductor die stacked on the first semiconductor die, a third semiconductor die disposed on the lifting supporter. The third semiconductor die vertically and partially overlapping with the second semiconductor die.

公开(公告)号：US20150270252A1

公开(公告)日：2015-09-24

申请号：US14734214

申请日：2015-06-09

Applicant: SK hynix Inc.

Inventor： Hee Min SHIN ,  Cheol Ho JOH ,  Eun Hye DO ,  Ji Eun KIM ,  Kyu Won LEE

IPC: H01L25/00 ,  H01L21/78 ,  H01L25/11

CPC classification number: H01L25/50 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/5389 ,  H01L24/18 ,  H01L24/19 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/117 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2924/00

Abstract: A stack package includes a cover film, a first package having a first semiconductor chip which is attached to the cover film, a first adhesive member which is formed to seal the first semiconductor chip and a surface of the cover film, and a first circuit pattern which is disposed over the first adhesive member and electrically connected with the first semiconductor chip; a second package disposed over the first package, having a second semiconductor chip which is electrically connected with the first circuit pattern, a second adhesive member which is formed to seal the second semiconductor chip, and a second circuit pattern which is formed over the second adhesive member, and a via formed to pass through the second circuit pattern and the second adhesive member and to be electrically connected with the first circuit pattern and the second circuit pattern.

Abstract translation: 叠层封装包括覆盖膜，具有附接到覆盖膜的第一半导体芯片的第一封装，形成为密封第一半导体芯片的第一粘合构件和覆盖膜的表面，以及第一电路图案 其设置在第一粘合构件上并与第一半导体芯片电连接; 第二封装，设置在所述第一封装上，具有与所述第一电路图案电连接的第二半导体芯片，形成为密封所述第二半导体芯片的第二粘合构件，以及形成在所述第二粘合剂上的第二电路图案 以及形成为穿过第二电路图案和第二粘合构件并且与第一电路图案和第二电路图案电连接的通孔。

公开(公告)号：US20220059504A1

公开(公告)日：2022-02-24

申请号：US17157648

申请日：2021-01-25

Applicant: SK hynix Inc.

Inventor： Eun Hye DO ,  Jong Hoon KIM

IPC: H01L25/065

Abstract: A semiconductor package includes: semiconductor chips being offset-stacked to expose edge regions adjacent to first side surfaces; chip pads disposed in each of the edge regions of the semiconductor chips, the chip pads including a plurality of first chip pads arranged in a first column and a plurality of second chip pads arranged in a second column; a horizontal common interconnector having one end connected to the second chip pad of a semiconductor chip of the semiconductor chips, and another end connected to the first chip pad of another semiconductor chip; and a vertical common interconnector having one end connected to the second chip pad of the uppermost semiconductor chip, which is electrically connected to the first chip pad of the uppermost semiconductor chip connected to the horizontal common interconnector.

公开(公告)号：US20150131255A1

公开(公告)日：2015-05-14

申请号：US14253554

申请日：2014-04-15

Applicant: SK hynix Inc.

Inventor： Eun Hye DO

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/18

CPC classification number: H01L24/49 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/1517 ,  H01L2924/15313 ,  H05K3/341 ,  H05K3/4015 ,  H05K3/4697 ,  H05K2201/0919 ,  H05K2201/09845 ,  H05K2201/10159 ,  H05K2201/10287 ,  H05K2201/10515 ,  Y02P70/613 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package may include: a substrate including a core layer having a first surface and a second surface which is opposite to the first surface, a wiring layer formed over the first and second surfaces and in an inside of the core layer, and having a first electrode disposed in the inside of the core layer and exposed from the core layer and a second electrode disposed over the first surface, and a passivation layer formed over the first and second surface of the core layer such that the first and the second electrodes are exposed; a first semiconductor chip disposed over the first surface of the core layer; a second semiconductor chip stacked over the first semiconductor chip; a first connection member for connecting the first semiconductor chip with the first electrode; and a second connection member for connecting the second semiconductor chip with the second electrode.

Abstract translation: 半导体封装可以包括：衬底，其包括具有第一表面的芯层和与第一表面相对的第二表面，布线层，形成在芯层的第一表面和第二表面之上，并且具有 设置在芯层的内部并从芯层露出的第一电极和设置在第一表面上的第二电极，以及形成在芯层的第一和第二表面上的钝化层，使得第一和第二电极为 裸露; 设置在所述芯层的第一表面上的第一半导体芯片; 堆叠在第一半导体芯片上的第二半导体芯片; 第一连接构件，用于将第一半导体芯片与第一电极连接; 以及用于将第二半导体芯片与第二电极连接的第二连接构件。