公开(公告)号：US20150270252A1

公开(公告)日：2015-09-24

申请号：US14734214

申请日：2015-06-09

Applicant: SK hynix Inc.

Inventor： Hee Min SHIN ,  Cheol Ho JOH ,  Eun Hye DO ,  Ji Eun KIM ,  Kyu Won LEE

IPC: H01L25/00 ,  H01L21/78 ,  H01L25/11

CPC classification number: H01L25/50 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/5389 ,  H01L24/18 ,  H01L24/19 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/117 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2924/00

Abstract: A stack package includes a cover film, a first package having a first semiconductor chip which is attached to the cover film, a first adhesive member which is formed to seal the first semiconductor chip and a surface of the cover film, and a first circuit pattern which is disposed over the first adhesive member and electrically connected with the first semiconductor chip; a second package disposed over the first package, having a second semiconductor chip which is electrically connected with the first circuit pattern, a second adhesive member which is formed to seal the second semiconductor chip, and a second circuit pattern which is formed over the second adhesive member, and a via formed to pass through the second circuit pattern and the second adhesive member and to be electrically connected with the first circuit pattern and the second circuit pattern.

Abstract translation: 叠层封装包括覆盖膜，具有附接到覆盖膜的第一半导体芯片的第一封装，形成为密封第一半导体芯片的第一粘合构件和覆盖膜的表面，以及第一电路图案 其设置在第一粘合构件上并与第一半导体芯片电连接; 第二封装，设置在所述第一封装上，具有与所述第一电路图案电连接的第二半导体芯片，形成为密封所述第二半导体芯片的第二粘合构件，以及形成在所述第二粘合剂上的第二电路图案 以及形成为穿过第二电路图案和第二粘合构件并且与第一电路图案和第二电路图案电连接的通孔。

公开(公告)号：US20130256887A1

公开(公告)日：2013-10-03

申请号：US13905254

申请日：2013-05-30

Applicant: SK hynix Inc.

Inventor： Kyu Won LEE ,  Cheol Ho JOH ,  Eun-Hye DO ,  Ji Eun KIM ,  Hee Min SHIN

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L21/561 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/03 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1064 ,  H01L2225/1076 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A stacked semiconductor package includes a semiconductor package module including a plurality of semiconductor packages each of which has a first surface, a second surface facing away from the first surface, side surfaces connecting the first surface and the second surface and through-holes formed on the side surfaces to pass through the first surface and the second surface and which are stacked such that their through-holes vertically connect with one another, and adhesive members which are formed between the semiconductor packages and attach the semiconductor packages to one another, a main substrate supporting the semiconductor package module and formed, on a third surface thereof facing the semiconductor package module, with main connection pads which are aligned with the through-holes, and conductive connection members formed in the through-holes and electrically connecting the semiconductor packages with the main connection pads.

Abstract translation: 堆叠半导体封装包括半导体封装模块，其包括多个半导体封装，每个半导体封装具有第一表面，背离第一表面的第二表面，连接第一表面和第二表面的侧表面和形成在第一表面上的通孔 侧表面通过第一表面和第二表面并且堆叠成使得它们的通孔彼此垂直连接;以及粘合构件，其形成在半导体封装之间并将半导体封装彼此附接，主基板 支撑半导体封装模块，并在其面向半导体封装模块的第三表面上形成与通孔对准的主连接焊盘，以及形成在通孔中的导电连接构件，并将半导体封装与 主连接垫

公开(公告)号：US20160379961A1

公开(公告)日：2016-12-29

申请号：US14882557

申请日：2015-10-14

Applicant: SK hynix Inc.

Inventor： Kyu Won LEE ,  Ki Ill MOON ,  Cheol Woo HAN

IPC: H01L25/065

CPC classification number: H01L25/0657 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/73253 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: Disclosed herein are semiconductor packages. A semiconductor package may include a substrate configured to include a first face and a second face opposite the first face and to have a recess formed in the first face. The semiconductor package may include a first semiconductor chip disposed on the bottom of the recess. The semiconductor package may include a second semiconductor chip disposed on the second face of the substrate. The semiconductor package may include a third semiconductor chip disposed over the first face of the substrate and the first semiconductor chip. The semiconductor package may include a fourth semiconductor chip disposed over the third semiconductor chip.

Abstract translation: 这里公开了半导体封装。 半导体封装可以包括被配置为包括第一面和与第一面相对的第二面的衬底，并且在第一面中形成凹部。 半导体封装可以包括设置在凹部底部的第一半导体芯片。 半导体封装可以包括设置在衬底的第二面上的第二半导体芯片。 半导体封装可以包括设置在衬底的第一面和第一半导体芯片上的第三半导体芯片。 半导体封装可以包括设置在第三半导体芯片上的第四半导体芯片。

公开(公告)号：US20140175638A1

公开(公告)日：2014-06-26

申请号：US13846713

申请日：2013-03-18

Applicant: SK HYNIX INC.

Inventor： Ji Eun KIM ,  Cheol Ho JOH ,  Hee Min SHIN ,  Kyu Won LEE ,  Chong Ho CHO

IPC: H01L23/498

CPC classification number: H01L23/49827 ,  H01L21/6836 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/78 ,  H01L24/92 ,  H01L25/043 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/0756 ,  H01L25/50 ,  H01L29/0657 ,  H01L2221/68327 ,  H01L2224/04042 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/49174 ,  H01L2224/73265 ,  H01L2224/78346 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10158 ,  H01L2924/1531 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The semiconductor package includes an upper semiconductor chip stacked on a package substrate and a support layer or a lower semiconductor chip disposed between the upper semiconductor chip and the package substrate. The upper semiconductor chip includes a protrusion downwardly extending from an edge thereof. The protrusion of the upper semiconductor chip is combined with a sidewall of the support layer or the lower semiconductor chip. Related methods are also provided.

Abstract translation: 半导体封装包括堆叠在封装衬底上的上半导体芯片和设置在上半导体芯片和封装衬底之间的支撑层或下半导体芯片。 上半导体芯片包括从其边缘向下延伸的突起。 上半导体芯片的突起与支撑层或下半导体芯片的侧壁组合。 还提供了相关方法。

公开(公告)号：US20140057369A1

公开(公告)日：2014-02-27

申请号：US13719082

申请日：2012-12-18

Applicant: SK HYNIX INC.

Inventor： Kyu Won LEE ,  Cheol-Ho JOH ,  Ji Eun KIM ,  Hee-Min SHIN ,  Chong Ho CHO

IPC: H01L21/48

CPC classification number: H01L21/4846 ,  H01L21/4867 ,  H01L23/3178 ,  H01L23/49838 ,  H01L23/49866 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/02311 ,  H01L2224/02317 ,  H01L2224/02375 ,  H01L2224/0332 ,  H01L2224/03515 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05554 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Methods of forming an interconnection line pattern using a screen printing technique. The method includes preparing a substrate having unevenness, aligning a stencil mask on the substrate, and printing a paste including materials for forming the interconnection line pattern on a convex portion of the unevenness formed on the substrate.

Abstract translation: 使用丝网印刷技术形成互连线图案的方法。 该方法包括制备具有凹凸的基板，使基板上的模板掩模对准，以及在形成在基板上的凹凸的凸部上印刷包括用于形成互连线图案的材料的浆料。