公开(公告)号：US20170162516A1

公开(公告)日：2017-06-08

申请号：US15159987

申请日：2016-05-20

Applicant: SK hynix Inc.

Inventor： Cheol Ho JOH

IPC: H01L23/552 ,  H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L21/78 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L23/552 ,  H01L21/565 ,  H01L21/568 ,  H01L21/78 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2224/83005 ,  H01L2224/85005 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/1443 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2224/45099

Abstract: A method of fabricating a semiconductor package is provided. The method includes providing a package substrate strip including chip mounting regions, bridge regions connecting the chip mounting regions to each other, and through slits disposed between the chip mounting regions. A side shielding part including a lower portion filling the through slits and an upper portion upwardly extending from the lower side shielding part to protrude from the package substrate strip is formed. Semiconductor chips are mounted on the chip mounting regions. Mold patterns are formed on the package substrate strip to cover the semiconductor chips and to expose a top surface of the side shielding part. A top shielding part is formed on the mold patterns to contact the side shielding part.

公开(公告)号：US20150008580A1

公开(公告)日：2015-01-08

申请号：US14083687

申请日：2013-11-19

Applicant: SK hynix Inc.

Inventor： Cheol Ho JOH

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L24/14 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2924/00

Abstract: The disclosure relates to a stacked package and a method for manufacturing the same. The stacked package includes: a lower package including a substrate formed with ball lands in a periphery of an upper surface thereof, a semiconductor chip mounted over the upper surface, first solder balls formed over the ball lands and each having a side surface cut along an edge of the substrate and a polished upper surface, and a mold part for molding the upper surface including the semiconductor chip and the first solder balls, the cutted side surfaces and polished upper surfaces being exposed by the mold part; and an upper package stacked over the lower package and provided with second solder balls bonded to the first solder balls.

Abstract translation: 本发明涉及堆叠式封装及其制造方法。 堆叠式封装包括：下部封装，其包括在其上表面的周边形成有球形焊盘的基板，安装在上表面上的半导体芯片，形成在所述球场上的第一焊球，并且每个具有侧表面沿着 基板的边缘和抛光的上表面，以及用于模制包括半导体芯片和第一焊球的上表面的模具部分，被切割的侧表面和抛光的上表面被模具部分露出; 以及堆叠在下封装上的上封装，并且设置有与第一焊球接合的第二焊球。

公开(公告)号：US20140175638A1

公开(公告)日：2014-06-26

申请号：US13846713

申请日：2013-03-18

Applicant: SK HYNIX INC.

Inventor： Ji Eun KIM ,  Cheol Ho JOH ,  Hee Min SHIN ,  Kyu Won LEE ,  Chong Ho CHO

IPC: H01L23/498

CPC classification number: H01L23/49827 ,  H01L21/6836 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/78 ,  H01L24/92 ,  H01L25/043 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/0756 ,  H01L25/50 ,  H01L29/0657 ,  H01L2221/68327 ,  H01L2224/04042 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/49174 ,  H01L2224/73265 ,  H01L2224/78346 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10158 ,  H01L2924/1531 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The semiconductor package includes an upper semiconductor chip stacked on a package substrate and a support layer or a lower semiconductor chip disposed between the upper semiconductor chip and the package substrate. The upper semiconductor chip includes a protrusion downwardly extending from an edge thereof. The protrusion of the upper semiconductor chip is combined with a sidewall of the support layer or the lower semiconductor chip. Related methods are also provided.

Abstract translation: 半导体封装包括堆叠在封装衬底上的上半导体芯片和设置在上半导体芯片和封装衬底之间的支撑层或下半导体芯片。 上半导体芯片包括从其边缘向下延伸的突起。 上半导体芯片的突起与支撑层或下半导体芯片的侧壁组合。 还提供了相关方法。

公开(公告)号：US20150279758A1

公开(公告)日：2015-10-01

申请号：US14461126

申请日：2014-08-15

Applicant: SK hynix Inc.

Inventor： Cheol Ho JOH

IPC: H01L23/31 ,  H01L23/495

CPC classification number: H01L23/3157 ,  H01L23/13 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/48091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: The semiconductor package includes: a substrate having a window and first and second bond fingers arranged over a first surface along a periphery of the window; a first semiconductor chip disposed within the window and having a plurality of first bonding pads arranged over edges of an upper surface; a plurality of first connection members electrically coupling the first bonding pads with the first bonding fingers; a second semiconductor chip disposed over the first semiconductor chip and the first surface of the substrate and a plurality of second bonding pads in the edges of the lower surface; a plurality of second connection members electrically coupling the second bonding pads with the second bonding fingers of the substrate adjacent to the second bonding pads; and an encapsulation member formed over the first surface of the substrate to cover side surfaces of the second semiconductor chip.

Abstract translation: 所述半导体封装包括：具有窗口的基板和沿着所述窗口的周边布置在第一表面上的第一和第二接合指状物; 第一半导体芯片，设置在所述窗口内并且具有布置在上表面的边缘上的多个第一接合焊盘; 多个第一连接构件，其将所述第一接合焊盘与所述第一接合指状物电耦合; 设置在所述第一半导体芯片和所述基板的所述第一表面上的第二半导体芯片和在所述下表面的边缘中的多个第二焊盘; 多个第二连接构件将所述第二接合焊盘与所述衬底的与所述第二接合焊盘相邻的所述第二接合指电性地耦合; 以及形成在所述基板的所述第一表面上以覆盖所述第二半导体芯片的侧表面的封装构件。

公开(公告)号：US20150270252A1

公开(公告)日：2015-09-24

申请号：US14734214

申请日：2015-06-09

Applicant: SK hynix Inc.

Inventor： Hee Min SHIN ,  Cheol Ho JOH ,  Eun Hye DO ,  Ji Eun KIM ,  Kyu Won LEE

IPC: H01L25/00 ,  H01L21/78 ,  H01L25/11

CPC classification number: H01L25/50 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/5389 ,  H01L24/18 ,  H01L24/19 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/117 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2924/00

Abstract: A stack package includes a cover film, a first package having a first semiconductor chip which is attached to the cover film, a first adhesive member which is formed to seal the first semiconductor chip and a surface of the cover film, and a first circuit pattern which is disposed over the first adhesive member and electrically connected with the first semiconductor chip; a second package disposed over the first package, having a second semiconductor chip which is electrically connected with the first circuit pattern, a second adhesive member which is formed to seal the second semiconductor chip, and a second circuit pattern which is formed over the second adhesive member, and a via formed to pass through the second circuit pattern and the second adhesive member and to be electrically connected with the first circuit pattern and the second circuit pattern.

Abstract translation: 叠层封装包括覆盖膜，具有附接到覆盖膜的第一半导体芯片的第一封装，形成为密封第一半导体芯片的第一粘合构件和覆盖膜的表面，以及第一电路图案 其设置在第一粘合构件上并与第一半导体芯片电连接; 第二封装，设置在所述第一封装上，具有与所述第一电路图案电连接的第二半导体芯片，形成为密封所述第二半导体芯片的第二粘合构件，以及形成在所述第二粘合剂上的第二电路图案 以及形成为穿过第二电路图案和第二粘合构件并且与第一电路图案和第二电路图案电连接的通孔。

公开(公告)号：US20140170812A1

公开(公告)日：2014-06-19

申请号：US13846640

申请日：2013-03-18

Applicant: SK HYNIX INC.

Inventor： Cheol Ho JOH

IPC: H01L21/50

CPC classification number: H01L24/85 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/78 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05553 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/787 ,  H01L2224/78745 ,  H01L2224/789 ,  H01L2224/83191 ,  H01L2224/85181 ,  H01L2224/85186 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/10161 ,  Y10T29/53178 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2224/4554

Abstract: There are proposed a method and apparatus for manufacturing a chip package in which bonding wires are coupled with contact pads in which an overhang holder holds and fixes portions of a surface adjacent to portions where the contact pads are located.

Abstract translation: 提出了一种用于制造芯片封装的方法和装置，其中，接合线与接触焊盘耦合，其中突出支架保持并固定与接触垫所在部分相邻的表面的部分。

公开(公告)号：US20130256887A1

公开(公告)日：2013-10-03

申请号：US13905254

申请日：2013-05-30

Applicant: SK hynix Inc.

Inventor： Kyu Won LEE ,  Cheol Ho JOH ,  Eun-Hye DO ,  Ji Eun KIM ,  Hee Min SHIN

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L21/561 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/03 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1064 ,  H01L2225/1076 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A stacked semiconductor package includes a semiconductor package module including a plurality of semiconductor packages each of which has a first surface, a second surface facing away from the first surface, side surfaces connecting the first surface and the second surface and through-holes formed on the side surfaces to pass through the first surface and the second surface and which are stacked such that their through-holes vertically connect with one another, and adhesive members which are formed between the semiconductor packages and attach the semiconductor packages to one another, a main substrate supporting the semiconductor package module and formed, on a third surface thereof facing the semiconductor package module, with main connection pads which are aligned with the through-holes, and conductive connection members formed in the through-holes and electrically connecting the semiconductor packages with the main connection pads.

Abstract translation: 堆叠半导体封装包括半导体封装模块，其包括多个半导体封装，每个半导体封装具有第一表面，背离第一表面的第二表面，连接第一表面和第二表面的侧表面和形成在第一表面上的通孔 侧表面通过第一表面和第二表面并且堆叠成使得它们的通孔彼此垂直连接;以及粘合构件，其形成在半导体封装之间并将半导体封装彼此附接，主基板 支撑半导体封装模块，并在其面向半导体封装模块的第三表面上形成与通孔对准的主连接焊盘，以及形成在通孔中的导电连接构件，并将半导体封装与 主连接垫