公开(公告)号：US11950417B2

公开(公告)日：2024-04-02

申请号：US17172458

申请日：2021-02-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wukang Kim ,  Sejun Park ,  Hyoje Bang ,  Jaeduk Lee ,  Junghoon Lee

IPC: H01L29/423 ,  H01L23/522 ,  H01L23/535 ,  H01L27/11524 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H01L23/535 ,  H10B43/35

Abstract: A semiconductor device including a stack structure including gate layers and interlayer insulating layers spaced apart in a vertical direction, a channel hole penetrating the stack structure in the vertical direction, a core region extending within the channel hole, a channel layer disposed on a side surface of the core region, a first dielectric layer, a data storage layer and a second dielectric layer, which are disposed between the channel layer and the gate layers, and a pad pattern disposed on the core region, in the channel hole, and in contact with the channel layer. A first horizontal distance between a side surface of a first portion of an uppermost gate layer and an outer side surface of the channel layer is greater than a second horizontal distance between a side surface of a second portion of the uppermost gate layer and an outer side surface of the pad pattern.

公开(公告)号：US11444094B2

公开(公告)日：2022-09-13

申请号：US16782737

申请日：2020-02-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sejun Park ,  Jaeduk Lee ,  Jaehoon Jang ,  Jin-Kyu Kang ,  Seungwan Hong ,  Okcheon Hong

IPC: H01L27/11582 ,  H01L27/11556 ,  G11C5/02

Abstract: A semiconductor memory device includes a stack structure including electrodes and insulating layers alternately stacked on a substrate, and a vertical channel structure penetrating the stack structure. The vertical channel structure includes a semiconductor pattern and a vertical insulating layer between the semiconductor pattern and the electrodes. The vertical insulating layer includes a charge storage layer, a filling insulating layer, and a tunnel insulating layer. The vertical insulating layer has a cell region between the semiconductor pattern and each electrode and a cell separation region between the semiconductor pattern and each insulating layer. A portion of the charge storage layer of the cell region is in physical contact with the tunnel insulating layer. The filling insulating layer is between the semiconductor pattern and a remaining portion of the charge storage layer of the cell region.

公开(公告)号：US09941135B2

公开(公告)日：2018-04-10

申请号：US14840114

申请日：2015-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sejun Park ,  Dohyung Kim ,  Jaihyung Won ,  Sangho Roh ,  Eunsol Shin ,  Seung Moo Lee ,  Gyuwan Choi

IPC: H01L21/308 ,  H01L21/311 ,  H01L21/762 ,  C23C16/26 ,  C23C16/56 ,  H01L21/02 ,  H01L29/423 ,  H01L27/108

CPC classification number: H01L21/3081 ,  C23C16/26 ,  C23C16/56 ,  H01L21/02115 ,  H01L21/02266 ,  H01L21/02274 ,  H01L21/31144 ,  H01L21/762 ,  H01L21/76224 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10888 ,  H01L29/4236

Abstract: A method of forming a hard mask layer on a substrate includes forming an amorphous carbon layer using nitrous oxide (N2O). A source of carbon and the nitrous oxide (N2O) are introduced to the substrate under a plasma ambient of an inert gas. The amorphous carbon layer has a nitrogen content ranging from about 0.05 at % to about 30 at % and an oxygen content ranging from about 0.05 at % to about 10 at %. In forming a semiconductor device, the hard mask layer is patterned, and a target layer beneath the hard mask layer is etched using the patterned hard mask layer as an etch mask.

公开(公告)号：US11699490B2

公开(公告)日：2023-07-11

申请号：US17220218

申请日：2021-04-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soyeong Gwak ,  Raeyoung Lee ,  Jinkyu Kang ,  Sejun Park ,  Changhwan Shin ,  Jaeduk Lee ,  Woojae Jang

IPC: G11C16/34 ,  G11C16/16 ,  G11C16/26 ,  G11C7/10 ,  G11C16/24 ,  G11C16/08

CPC classification number: G11C16/16 ,  G11C7/106 ,  G11C7/1087 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/349

Abstract: An operating method of a storage device includes reading a wear-out pattern of a memory block when a controller determines the memory block is a re-use memory block of a non-volatile memory device; selecting an operation mode corresponding to the read wear-out pattern using the controller; and transmitting the selected operation mode to the non-volatile memory device using the controller.

公开(公告)号：US11257841B2

公开(公告)日：2022-02-22

申请号：US16787195

申请日：2020-02-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-Kyu Kang ,  Woojae Jang ,  Changsub Lee ,  Sejun Park ,  Jaeduk Lee ,  Jung Hoon Lee

IPC: H01L27/11582 ,  H01L29/792 ,  H01L29/423 ,  H01L29/78

Abstract: A three-dimensional semiconductor memory device including a stack structure including gate structures and first dielectric patterns alternately stacked, a vertical channel penetrating the stack structure, and a charge storage layer extending from between the vertical channel and the first gate structures to between the vertical channel and the first dielectric patterns. The gate structures include first gate structures having a top surface and a bottom surface facing each other and having different width. The charge storage layer includes first segments between the vertical channel and the first gate structures, and second segments between the vertical channel and the first dielectric patterns. A thickness of the first segments is greater than a thickness of the second segments. One of the width of the top surface and the width of bottom surface of each first gate structure is the same as that of a first dielectric pattern on the first gate structure.

公开(公告)号：US10128266B2

公开(公告)日：2018-11-13

申请号：US15592030

申请日：2017-05-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung Hoon Lee ,  Keejeong Rho ,  Sejun Park ,  Jinhyun Shin ,  Dong-Sik Lee ,  Woong-Seop Lee

IPC: H01L27/11582 ,  H01L23/528 ,  G11C16/08 ,  H01L27/11556 ,  H01L27/1157

Abstract: A semiconductor device includes lower and upper selection lines, a cell gate structure, a lower dummy structure and an upper dummy structure. The cell gate structure is between the lower and upper selection lines and includes cell gate electrodes stacked in a first direction. The lower dummy structure is between the lower selection line and the cell gate structure and includes a lower dummy gate line spaced from a lowermost one of the cell gate electrodes by a first distance. The upper dummy structure is between the upper selection line and the cell gate structure and includes an upper dummy gate line spaced from an uppermost one of the cell gate electrodes by a second distance. The cell gate electrodes are spaced by a third distance less than each of the first and second distances.

公开(公告)号：US11894079B2

公开(公告)日：2024-02-06

申请号：US17384219

申请日：2021-07-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeji Lee ,  Raeyoung Lee ,  Jinkyu Kang ,  Sejun Park ,  Jaeduk Lee

IPC: G11C16/34 ,  G11C16/26 ,  G11C16/10

CPC classification number: G11C16/3463 ,  G11C16/102 ,  G11C16/26 ,  G11C16/3404

Abstract: A memory controller includes an over-program controller that preprograms and then erases the memory cells such that each of the memory cells has a first threshold voltage level, wherein fast cells are detected among the memory cells according to a threshold voltage less than or equal to a second threshold voltage less than the first threshold voltage, and a processor that generates fast cell information identifying the fast cells among the memory cells and stores the fast cell information in a buffer. The over-program controller controls the over-programming of the fast cells and normal programming of normal cells among the memory cells based on the fast cell information stored in the buffer.

公开(公告)号：US20200303390A1

公开(公告)日：2020-09-24

申请号：US16782737

申请日：2020-02-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sejun Park ,  Jaeduk Lee ,  Jaehoon Jang ,  Jin-Kyu Kang ,  Seungwan Hong ,  Okcheon Hong

IPC: H01L27/11556 ,  H01L27/11582 ,  G11C5/02

Abstract: A semiconductor memory device includes a stack structure including electrodes and insulating layers alternately stacked on a substrate, and a vertical channel structure penetrating the stack structure. The vertical channel structure includes a semiconductor pattern and a vertical insulating layer between the semiconductor pattern and the electrodes. The vertical insulating layer includes a charge storage layer, a filling insulating layer, and a tunnel insulating layer. The vertical insulating layer has a cell region between the semiconductor pattern and each electrode and a cell separation region between the semiconductor pattern and each insulating layer. A portion of the charge storage layer of the cell region is in physical contact with the tunnel insulating layer. The filling insulating layer is between the semiconductor pattern and a remaining portion of the charge storage layer of the cell region.

公开(公告)号：US20240206177A1

公开(公告)日：2024-06-20

申请号：US18591076

申请日：2024-02-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wukang Kim ,  Sejun Park ,  Hyoje Bang ,  Jaeduk Lee ,  Junghoon Lee

IPC: H10B43/27 ,  H01L23/522 ,  H01L23/535 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H01L23/535 ,  H10B43/35

Abstract: A semiconductor device including a stack structure including gate layers and interlayer insulating layers spaced apart in a vertical direction, a channel hole penetrating the stack structure in the vertical direction, a core region extending within the channel hole, a channel layer disposed on a side surface of the core region, a first dielectric layer, a data storage layer and a second dielectric layer, which are disposed between the channel layer and the gate layers, and a pad pattern disposed on the core region, in the channel hole, and in contact with the channel layer. A first horizontal distance between a side surface of a first portion of an uppermost gate layer and an outer side surface of the channel layer is greater than a second horizontal distance between a side surface of a second portion of the uppermost gate layer and an outer side surface of the pad pattern.

公开(公告)号：US20210408037A1

公开(公告)日：2021-12-30

申请号：US17172458

申请日：2021-02-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wukang Kim ,  Sejun Park ,  Hyoje Bang ,  Jaeduk Lee ,  Junghoon Lee

IPC: H01L27/11582 ,  H01L23/522 ,  H01L23/535

Abstract: A semiconductor device including a stack structure including gate layers and interlayer insulating layers spaced apart in a vertical direction, a channel hole penetrating the stack structure in the vertical direction, a core region extending within the channel hole, a channel layer disposed on a side surface of the core region, a first dielectric layer, a data storage layer and a second dielectric layer, which are disposed between the channel layer and the gate layers, and a pad pattern disposed on the core region, in the channel hole, and in contact with the channel layer. A first horizontal distance between a side surface of a first portion of an uppermost gate layer and an outer side surface of the channel layer is greater than a second horizontal distance between a side surface of a second portion of the uppermost gate layer and an outer side surface of the pad pattern.