公开(公告)号：US20170162683A1

公开(公告)日：2017-06-08

申请号：US15437559

申请日：2017-02-21

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo NAKAYAMA ,  Hironobu MIYAMOTO ,  Yasuhiro OKAMOTO ,  Yoshinao MIURA ,  Takashi INOUE

IPC: H01L29/778 ,  H01L29/15 ,  H01L29/423 ,  H01L29/40 ,  H01L23/535 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/027 ,  H01L29/205 ,  H01L29/06

CPC classification number: H01L29/7787 ,  H01L21/0274 ,  H01L21/3065 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/1066 ,  H01L29/1075 ,  H01L29/1087 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786

Abstract: A semiconductor device includes a first nitride semiconductor layer formed over a substrate, a second nitride semiconductor layer formed over the first nitride semiconductor layer, a third nitride semiconductor layer formed over the second nitride semiconductor layer, a fourth nitride semiconductor layer formed over the third nitride semiconductor layer, a trench that penetrates the fourth nitride semiconductor layer and reaches as far as the third nitride semiconductor layer, a gate electrode disposed by way of a gate insulation film in the trench, a first electrode and a second electrode formed respectively over the fourth nitride semiconductor layer on both sides of the gate electrode, and a coupling portion for coupling the first electrode and the first nitride semiconductor layer.

公开(公告)号：US20170271326A1

公开(公告)日：2017-09-21

申请号：US15610329

申请日：2017-05-31

Applicant: Renesas Electronics Corporation

Inventor： Yoshinao MIURA

IPC: H01L27/06 ,  H01L23/482 ,  H01L23/528 ,  H01L27/02 ,  H01L21/8252

CPC classification number: H01L27/0629 ,  H01L21/8252 ,  H01L23/4824 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0605 ,  H01L2924/00 ,  H01L2924/0002

Abstract: A semiconductor device includes a substrate, a plurality of transistors formed on a transistor region of the substrate, a plurality of diodes formed on a diode region of the substrate, the transistors and the diodes being arranged in a first direction, a first line formed over the substrate and extending between the transistors and the diodes, a plurality of first branch lines extending from the first line in the first direction to form a drain electrode of the transistors, and a plurality of second branch lines extending from the first line in the first direction to form an anode electrode of the diodes.

公开(公告)号：US20150221758A1

公开(公告)日：2015-08-06

申请号：US14590433

申请日：2015-01-06

Applicant: Renesas Electronics Corporation

Inventor： Yoshinao MIURA ,  Tatsuo NAKAYAMA ,  Takashi INOUE ,  Hironobu MIYAMOTO

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/205 ,  H01L29/20 ,  H01L29/201

CPC classification number: H01L29/7787 ,  H01L29/1087 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7783

Abstract: To provide a semiconductor device having improved characteristics. The semiconductor device has, over a substrate thereof, a first buffer layer (GaN), a second buffer layer (AlGaN), a channel layer, and a barrier layer, a trench penetrating through the barrier layer and reaching the middle of the channel layer, a gate electrode placed in the trench via a gate insulating film, and a source electrode and a drain electrode formed on both sides of the gate electrode respectively. By a coupling portion in a through-hole reaching the first buffer layer, the buffer layer and the source electrode are electrically coupled to each other. Due to a two-dimensional electron gas produced in the vicinity of the interface between these two buffer layers, the semiconductor device can have an increased threshold voltage and improved normally-off characteristics.

Abstract translation: 提供具有改进特性的半导体器件。 半导体器件在其衬底上具有第一缓冲层（GaN），第二缓冲层（AlGaN），沟道层和势垒层，穿过阻挡层并到达沟道层中间的沟槽 通过栅极绝缘膜放置在沟槽中的栅电极，以及分别形成在栅极两侧的源电极和漏电极。 通过到达第一缓冲层的通孔中的耦合部分，缓冲层和源电极彼此电耦合。 由于在这两个缓冲层之间的界面附近产生的二维电子气，所以半导体器件可以具有增加的阈值电压和改善的常关特性。

公开(公告)号：US20180308968A1

公开(公告)日：2018-10-25

申请号：US15904701

申请日：2018-02-26

Applicant: Renesas Electronics Corporation

Inventor： Yoshinao MIURA ,  Hironobu MIYAMOTO

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/06 ,  H01L29/417 ,  H01L29/47 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/7787 ,  H01L21/02389 ,  H01L21/0254 ,  H01L21/0273 ,  H01L21/28581 ,  H01L21/30621 ,  H01L21/32139 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41758 ,  H01L29/475 ,  H01L29/66462

Abstract: Characteristics of a semiconductor device are improved.A semiconductor device of the present invention includes a buffer layer composed of a first nitride semiconductor layer, a channel layer composed of a second nitride semiconductor layer, and a barrier layer composed of a third nitride semiconductor layer, which are sequentially laminated, and a cap layer composed of a fourth nitride semiconductor layer of mesa type, which is formed over the barrier layer. The semiconductor device also includes a source electrode formed on one side of the cap layer, a drain electrode formed on the other side of the cap layer, and a first gate electrode formed over the cap layer. The first gate electrode and the cap layer are Schottky-joined. A Schottky gate electrode (the first gate electrode) is provided over the cap layer in this way, so that when a gate voltage is applied, an electric field is applied to the entire cap layer and a depletion layer spreads. Therefore, it is possible to suppress a gate leakage current.

公开(公告)号：US20170077013A1

公开(公告)日：2017-03-16

申请号：US15341332

申请日：2016-11-02

Applicant: Renesas Electronics Corporation

Inventor： Akira MATSUMOTO ,  Yoshinao MIURA ,  Yasutaka NAKASHIBA

IPC: H01L23/495 ,  H01L23/00 ,  H01L29/778 ,  H01L29/20 ,  H01L29/205

CPC classification number: H01L23/49562 ,  H01L23/4824 ,  H01L23/485 ,  H01L23/492 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49548 ,  H01L23/49575 ,  H01L23/50 ,  H01L23/528 ,  H01L23/5283 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0203 ,  H01L27/0605 ,  H01L27/088 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/78 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/45014 ,  H01L2224/451 ,  H01L2224/4805 ,  H01L2224/4813 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/1033 ,  H01L2924/10344 ,  H01L2924/13064 ,  H01L2924/30101 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: Disclosed is a semiconductor device in which a resistance component resulting from wiring is reduced. A plurality of transistor units are arranged side by side in a first direction, each of which has a plurality of transistors. The gate electrodes of the transistors extend in the first direction. First source wiring extends between first transistor unit and second transistor unit, and first drain wiring extends between the second transistor unit and third transistor unit. Second drain wiring extends on the side of the first transistor unit opposite to the side where the first source wiring extends, and second source wiring extends on the side of the third transistor unit opposite to the side where the second drain wiring extends.

Abstract translation: 公开了一种半导体器件，其中由布线产生的电阻分量减小。 多个晶体管单元沿第一方向并排布置，每个晶体管单元具有多个晶体管。 晶体管的栅电极沿第一方向延伸。 第一源极布线在第一晶体管单元和第二晶体管单元之间延伸，并且第一漏极布线在第二晶体管单元和第三晶体管单元之间延伸。 第二漏极布线在第一晶体管单元的与第一源极布线延伸的一侧相反的一侧延伸，并且第二源极布线在与第二漏极布线延伸的一侧相反的一侧延伸。

公开(公告)号：US20160233211A1

公开(公告)日：2016-08-11

申请号：US14970627

申请日：2015-12-16

Applicant: Renesas Electronics Corporation

Inventor： Yoshinao MIURA ,  Hironobu MIYAMOTO ,  Yasuhiro OKAMOTO

IPC: H01L27/06 ,  H01L29/872 ,  H01L29/778 ,  H01L29/20 ,  H01L29/205

CPC classification number: H01L27/0629 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0203 ,  H01L27/0207 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/7787 ,  H01L29/872 ,  H01L2224/0603 ,  H01L2224/45014 ,  H01L2224/45144 ,  H01L2224/4846 ,  H01L2224/4903 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

Abstract: The ringing of a switching waveform of a semiconductor device is restrained. For example, an interconnect (L5) is laid which functions as a source of a power transistor (Q3) and a cathode of a diode (D4), and further functioning as a drain of a power transistor (Q4) and an anode of a diode (D3). In other words, a power transistor and a diode coupled to this power transistor in series are formed in the same semiconductor chip; and further an interconnect functioning as a drain of the power transistor and an interconnect functioning as an anode of the diode are made common to each other. This structure makes it possible to decrease a parasite inductance between the power transistor and the diode coupled to each other in series.

Abstract translation: 限制了半导体器件的开关波形的振铃。 例如，布置了互连（L5），其用作功率晶体管（Q3）的源极和二极管（D4）的阴极，并且还用作功率晶体管（Q4）的漏极和功率晶体管 二极管（D3）。 换句话说，串联在该功率晶体管上的功率晶体管和二极管形成在同一半导体芯片中; 并且另外用作功率晶体管的漏极的互连和用作二极管的阳极的互连彼此共同。 这种结构使得可以降低功率晶体管和彼此串联耦合的二极管之间的寄生电感。

公开(公告)号：US20150280571A1

公开(公告)日：2015-10-01

申请号：US14742045

申请日：2015-06-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Koji TATENO ,  Takahiro NOMIYAMA ,  Yoshinao MIURA ,  Hideo ISHII

IPC: H02M3/158

CPC classification number: H02M3/158 ,  H02M1/38 ,  H02M3/1588 ,  Y02B70/1466

Abstract: Disclosed is a power conversion circuit that suppresses the flow of a through current to a switching element based on a normally-on transistor. The power conversion circuit includes a high-side transistor and a low-side transistor, which are series-coupled to each other to form a half-bridge circuit, and two drive circuits, which complementarily drive the gate of the high-side transistor and of the low-side transistor. The high-side transistor is a normally-off transistor. The low-side transistor is a normally-on transistor.

Abstract translation: 公开了一种功率转换电路，其抑制基于常通晶体管的开关元件的通流电流。 功率转换电路包括彼此串联耦合以形成半桥电路的高侧晶体管和低侧晶体管，以及互补驱动高边晶体管的栅极的两个驱动电路，以及 的低端晶体管。 高边晶体管是常关晶体管。 低端晶体管是常开晶体管。

公开(公告)号：US20150035080A1

公开(公告)日：2015-02-05

申请号：US14339013

申请日：2014-07-23

Applicant: Renesas Electronics Corporation

Inventor： Akira Matsumoto ,  Yoshinao MIURA ,  Yasutaka NAKASHIBA

IPC: H01L27/088 ,  H01L23/50 ,  H01L27/02

CPC classification number: H01L23/49562 ,  H01L23/4824 ,  H01L23/485 ,  H01L23/492 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49548 ,  H01L23/49575 ,  H01L23/50 ,  H01L23/528 ,  H01L23/5283 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0203 ,  H01L27/0605 ,  H01L27/088 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/78 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/45014 ,  H01L2224/451 ,  H01L2224/4805 ,  H01L2224/4813 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/1033 ,  H01L2924/10344 ,  H01L2924/13064 ,  H01L2924/30101 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: Disclosed is a semiconductor device in which a resistance component resulting from wiring is reduced. A plurality of transistor units are arranged side by side in a first direction (Y direction in the view), each of which has a plurality of transistors. The gate electrodes of the transistors extend in the first direction. First source wiring extends between first transistor unit and second transistor unit, and first drain wiring extends between the second transistor unit and third transistor unit. Second drain wiring extends on the side of the first transistor unit opposite to the side where the first source wiring extends, and second source wiring extends on the side of the third transistor unit opposite to the side where the second drain wiring extends.

Abstract translation: 公开了一种半导体器件，其中由布线产生的电阻分量减小。 多个晶体管单元沿着第一方向（视图中的Y方向）并排布置，每个晶体管单元具有多个晶体管。 晶体管的栅电极沿第一方向延伸。 第一源极布线在第一晶体管单元和第二晶体管单元之间延伸，并且第一漏极布线在第二晶体管单元和第三晶体管单元之间延伸。 第二漏极布线在第一晶体管单元的与第一源极布线延伸的一侧相反的一侧延伸，并且第二源极布线在与第二漏极布线延伸的一侧相反的一侧延伸。

公开(公告)号：US20180097070A1

公开(公告)日：2018-04-05

申请号：US15679600

申请日：2017-08-17

Applicant: Renesas Electronics Corporation

Inventor： Yoshinao MIURA ,  Hironobu MIYAMOTO

IPC: H01L29/20 ,  H01L23/66 ,  H01L29/778 ,  H01L29/205

CPC classification number: H01L29/2003 ,  H01L23/66 ,  H01L28/20 ,  H01L28/40 ,  H01L29/1066 ,  H01L29/205 ,  H01L29/41758 ,  H01L29/42336 ,  H01L29/4236 ,  H01L29/7783 ,  H01L29/7787 ,  H01L29/788 ,  H01L29/94

Abstract: A semiconductor device includes a channel layer formed over a substrate, a barrier layer formed on the channel layer and a gate electrode. A second gate electrode section is formed on the gate electrode via a gate insulating film. It becomes possible to make an apparent threshold voltage applied to the second gate electrode of a MISFET higher than an original threshold voltage applied to the gate electrode for forming a channel under the gate electrode by providing an MIM section configured by the gate electrode, the gate insulating film and the second gate electrode in this way.

公开(公告)号：US20170278798A1

公开(公告)日：2017-09-28

申请号：US15467051

申请日：2017-03-23

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshinao MIURA

IPC: H01L23/535 ,  H01L29/423 ,  H01L29/417 ,  H01L29/06 ,  H01L27/088

CPC classification number: H01L23/535 ,  H01L23/4824 ,  H01L23/49562 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/41775 ,  H01L29/42356 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/452 ,  H01L29/7786 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/4846 ,  H01L2224/49175

Abstract: An object of the present invention is to shorten the switching delay time of a semiconductor device.Transistor units are provided between a source bus line and a drain bus line that are provided apart from each other in a first direction, and a plurality of gate electrodes that extends in the first direction and is provided apart from each other in a second direction orthogonal to the first direction is provided in the transistor units. One ends of the gate electrodes on the source bus line side are coupled by a gate connection line extending in the second direction, and a gate bus line electrically coupled to the gate connection line is provided above the gate connection line. The gate electrodes and the gate connection line are formed using a wiring layer of the first layer, the source bus line and the drain bus line are formed using a wiring layer of the second layer, and the gate bus line is formed using a wiring layer of the third layer.