Abstract:
A cell protection system includes a charge control MOSFET 21, a charge current detection MOSFET 23, a discharge control MOSFET 20, a discharge current detection MOSFET 22, a charge current detection resistance 19, a discharge current detection resistance 16 and a control circuit. The MOSFET 23 has a drain and a gate common with the MOSFET 21. The MOSFET 20 has a drain common with the MOSFET 21. The MOSFET 22 has a drain and a gate common with the MOSFET 20. The resistances 19 and 16 are provided in correspondence to the MOSFETs 23 and 22, respectively. The control circuit generates a gate control signal for the MOSFETs 21 and 23 by using the resistance 19 and generates a gate control signal for the MOSFETs 20 and 22 by using the resistance 16.
Abstract:
A first MOSFET is formed in a first region of a chip, and a second MOSFET is formed in a second region thereof. A first source terminal and a first gate terminal are formed in the first region. In the second region, a second source terminal and a second gate terminal are arranged so as to be aligned substantially parallel to a direction in which the first source terminal and the first gate terminal are aligned. A temperature detection diode is arranged between the first source terminal and the second source terminal. A first terminal and a second terminal of the temperature detection diode are aligned in a first direction substantially parallel to a direction in which the first source terminal and the first gate terminal are aligned or in a second direction substantially perpendicular thereto.
Abstract:
A cell protection system includes a charge control MOSFET 21, a charge current detection MOSFET 23, a discharge control MOSFET 20, a discharge current detection MOSFET 22, a charge current detection resistance 19, a discharge current detection resistance 16 and a control circuit. The MOSFET 23 has a drain and a gate common with the MOSFET 21. The MOSFET 20 has a drain common with the MOSFET 21. The MOSFET 22 has a drain and a gate common with the MOSFET 20. The resistances 19 and 16 are provided in correspondence to the MOSFETs 23 and 22, respectively. The control circuit generates a gate control signal for the MOSFETs 21 and 23 by using the resistance 19 and generates a gate control signal for the MOSFETs 20 and 22 by using the resistance 16.
Abstract:
Miniaturization of a multiphase type power supply device can be achieved. A power supply control unit in which, for example, a microcontroller unit, a memory unit and an analog controller unit are formed over a single chip, a plurality of PWM-equipped drive units, and a plurality of inductors configure a multiphase power supply. The microcontroller unit outputs clock signals each having a frequency and a phase defined based on a program on the memory unit to the respective PWM-equipped drive units. The analog controller unit detects a difference between a voltage value of a load and a target voltage value acquired via a serial interface and outputs an error amp signal therefrom. Each of the PWM-equipped drive units drives each inductor by a peak current control system using the clock signal and the error amp signal.
Abstract:
Disclosed is a power conversion circuit that suppresses the flow of a through current to a switching element based on a normally-on transistor. The power conversion circuit includes a high-side transistor and a low-side transistor, which are series-coupled to each other to form a half-bridge circuit, and two drive circuits, which complementarily drive the gate of the high-side transistor and of the low-side transistor. The high-side transistor is a normally-off transistor. The low-side transistor is a normally-on transistor.
Abstract:
A first MOSFET is formed in a first region of a chip, and a second MOSFET is formed in a second region thereof. A first source terminal and a first gate terminal are formed in the first region. In the second region, a second source terminal and a second gate terminal are arranged so as to be aligned substantially parallel to a direction in which the first source terminal and the first gate terminal are aligned. A temperature detection diode is arranged between the first source terminal and the second source terminal. A first terminal and a second terminal of the temperature detection diode are aligned in a first direction substantially parallel to a direction in which the first source terminal and the first gate terminal are aligned or in a second direction substantially perpendicular thereto.