公开(公告)号：US20140152282A1

公开(公告)日：2014-06-05

申请号：US14084590

申请日：2013-11-19

Applicant: Renesas Electronics Corporation

Inventor： Kyoichi HOSOKAWA ,  Ryotaro KUDO ,  Toshio NAGASAWA ,  Koji TATENO

IPC: H02M3/158

CPC classification number: H02M3/1588 ,  G05F1/44 ,  H02M7/538 ,  H03F3/217 ,  H03F2200/351 ,  H03F2200/78 ,  H03K17/063 ,  H03K17/687 ,  Y02B70/1466

Abstract: In a switching power source which controls a current which flows in an inductor through a switching element which performs a switching operation in response to a PWM signal, and forms an output voltage by a capacitor which is provided in series in the inductor, a booster circuit which is constituted of a bootstrap capacity and a MOSFET is provided between an output node of the switching element and a predetermined voltage terminal. The boosted voltage is used as an operational voltage of a driving circuit of the switching element, another source/drain region and a substrate gate are connected with each other, and a junction diode between one source/drain region and the substrate gate is inversely directed with respect to the boosted voltage which is formed by the bootstrap capacity.

Abstract translation: 在开关电源中，其通过响应于PWM信号进行开关动作的开关元件来控制在电感器中流动的电流，并且通过串联设置在电感器中的电容器形成输出电压， 在开关元件的输出节点和预定的电压端子之间设置由自举电容构成的MOSFET和MOSFET。 升压电压用作开关元件的驱动电路的工作电压，另一个源极/漏极区域和衬底栅极彼此连接，并且在一个源极/漏极区域和衬底栅极之间的结二极管被反向导向 相对于由自举容量形成的升压电压。

公开(公告)号：US20180248492A1

公开(公告)日：2018-08-30

申请号：US15965178

申请日：2018-04-27

Applicant: Renesas Electronics Corporation

Inventor： Daisuke KONDO ,  Koji TATENO ,  Chang LIU ,  Nao NAGATA

IPC: H02M5/458 ,  H01L29/00 ,  H02M1/08 ,  H03K17/12 ,  H03K17/567 ,  H03K17/61 ,  H03K17/691 ,  H03K17/795

CPC classification number: H02M5/458 ,  H01L29/00 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/4238 ,  H01L29/7396 ,  H01L29/7397 ,  H02M1/08 ,  H03K17/127 ,  H03K17/168 ,  H03K17/567 ,  H03K17/61 ,  H03K17/691 ,  H03K17/7955 ,  H03K2217/0081

Abstract: A power conversion device includes a high-side transistor including an IGBT, a low-side transistor including an IGBT, and having a collector coupled to an emitter of the high-side transistor, a high-side driver configured to drive the high-side transistor; and a low-side driver configured to drive the low-side transistor, wherein each of the high-side transistor and the low-side transistor includes a first trench gate electrode arranged in an active cell region, and electrically connected to a gate, and a second trench gate electrode and a third trench gate electrode, each of which is arranged at intervals on both sides of the first trench gate electrode, and electrically connected to the emitter in the active cell region. The high-side driver includes a first pull-up transistor configured to apply a first voltage as a positive voltage to the gate, based on the emitter of the high-side transistor and a first pull-down transistor.

公开(公告)号：US20140176093A1

公开(公告)日：2014-06-26

申请号：US14064522

申请日：2013-10-28

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takahiro NOMIYAMA ,  Koji TATENO ,  Daisuke KONDO

IPC: H02M3/158

CPC classification number: H02M3/158 ,  H01L2224/0603 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H02M2001/0058 ,  H03K17/122 ,  H03K17/164 ,  H03K2217/0036 ,  H03K2217/0063 ,  H03K2217/0072 ,  Y02B70/1491

Abstract: A switching loss is reduced by reducing a deviation from the operational principle of zero-volt switching (ZVS). A semiconductor integrated circuit includes high-side switch elements Q11 and Q12, a low-side switch element Q2, and a controller CNT. A decoupling capacitance Cin is coupled between one end of a high-side element and an earth potential, and the high-side element includes the first and second transistors Q11 and Q12 coupled in parallel. In changing the high-side elements from an on-state to an off-state, CNT controls Q12 from an on-state to an off-state by delaying Q12 relative to Q11. Q11 and Q12 are divided into a plurality of parts inside a semiconductor chip Chip 1, a plurality of partial first transistors formed by dividing Q11 and a plurality of partial second transistors formed by dividing Q12 are alternately arranged in an arrangement direction of Q11 and Q12, inside the semiconductor chip Chip 1.

Abstract translation: 通过减少与零电压开关（ZVS）的工作原理的偏差来减少开关损耗。 半导体集成电路包括高侧开关元件Q11和Q12，低侧开关元件Q2和控制器CNT。 去耦电容Cin耦合在高侧元件的一端和地电位之间，高侧元件包括并联耦合的第一和第二晶体管Q11和Q12。 在将高端元件从导通状态切换到截止状态时，CNT通过相对于Q11延迟Q12，将Q12从导通状态切换到关闭状态。 Q11和Q12被分成半导体芯片芯片1内的多个部分，通过划分Q11而形成的多个局部第一晶体管和由Q12分割成的多个部分第二晶体管沿Q11和Q12的排列方向交替布置， 在半导体芯片芯片1内。

公开(公告)号：US20140173302A1

公开(公告)日：2014-06-19

申请号：US14187502

申请日：2014-02-24

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Ryotaro KUDO ,  Tomoaki UNO ,  Koji TATENO ,  Hideo ISHII ,  Kazuyuki UMEZU ,  Koji SAIKUSA

IPC: H02M3/158 ,  G06F1/26

CPC classification number: H02M3/158 ,  G06F1/26 ,  H02M3/1584 ,  H02M2003/1586

Abstract: Miniaturization of a multiphase type power supply device can be achieved. A power supply control unit in which, for example, a microcontroller unit, a memory unit and an analog controller unit are formed over a single chip, a plurality of PWM-equipped drive units, and a plurality of inductors configure a multiphase power supply. The microcontroller unit outputs clock signals each having a frequency and a phase defined based on a program on the memory unit to the respective PWM-equipped drive units. The analog controller unit detects a difference between a voltage value of a load and a target voltage value acquired via a serial interface and outputs an error amp signal therefrom. Each of the PWM-equipped drive units drives each inductor by a peak current control system using the clock signal and the error amp signal.

Abstract translation: 可以实现多相电源装置的小型化。 电源控制单元，其中例如在单个芯片上形成微控制器单元，存储单元和模拟控制器单元，多个配备PWM的驱动单元和多个电感器构成多相电源。 微控制器单元输出每个具有基于存储器单元上的程序定义的频率和相位到相应的配备有PWM的驱动单元的时钟信号。 模拟控制器单元检测负载的电压值与通过串行接口获取的目标电压值之间的差值，并输出误差放大器信号。 每个配备PWM的驱动单元通过使用时钟信号和误差放大器信号的峰值电流控制系统驱动每个电感器。

公开(公告)号：US20170287802A1

公开(公告)日：2017-10-05

申请号：US15430455

申请日：2017-02-11

Applicant: Renesas Electronics Corporation

Inventor： Hideo NUMABE ,  Koji TATENO ,  Yusuke OJIMA ,  Yoshihiko YOKOI ,  Shinya ISHIDA ,  Hitoshi MATSUURA

IPC: H01L23/34 ,  H01L23/528 ,  H01L29/06 ,  H01L23/522 ,  H01L23/532 ,  H01L21/285 ,  H01L21/311 ,  H01L21/8234 ,  H01L21/306 ,  H01L21/265 ,  H01L21/3205 ,  H03K17/16 ,  H01L49/02

CPC classification number: H01L23/34 ,  H01L21/26513 ,  H01L21/2855 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/32055 ,  H01L21/823412 ,  H01L23/5228 ,  H01L23/5286 ,  H01L23/53271 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/0692 ,  H01L29/7393 ,  H01L29/74 ,  H01L29/78 ,  H01L29/861 ,  H03K17/16 ,  H03K2017/0806 ,  H03K2217/0027 ,  H03K2217/0063 ,  H03K2217/0072

Abstract: A semiconductor device includes a power device and a temperature detection diode. The semiconductor device has a device structure configured to insulate between a power lien of the power device and the temperature detection diode.

公开(公告)号：US20150280571A1

公开(公告)日：2015-10-01

申请号：US14742045

申请日：2015-06-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Koji TATENO ,  Takahiro NOMIYAMA ,  Yoshinao MIURA ,  Hideo ISHII

IPC: H02M3/158

CPC classification number: H02M3/158 ,  H02M1/38 ,  H02M3/1588 ,  Y02B70/1466

Abstract: Disclosed is a power conversion circuit that suppresses the flow of a through current to a switching element based on a normally-on transistor. The power conversion circuit includes a high-side transistor and a low-side transistor, which are series-coupled to each other to form a half-bridge circuit, and two drive circuits, which complementarily drive the gate of the high-side transistor and of the low-side transistor. The high-side transistor is a normally-off transistor. The low-side transistor is a normally-on transistor.

Abstract translation: 公开了一种功率转换电路，其抑制基于常通晶体管的开关元件的通流电流。 功率转换电路包括彼此串联耦合以形成半桥电路的高侧晶体管和低侧晶体管，以及互补驱动高边晶体管的栅极的两个驱动电路，以及 的低端晶体管。 高边晶体管是常关晶体管。 低端晶体管是常开晶体管。