公开(公告)号：US20180183432A1

公开(公告)日：2018-06-28

申请号：US15796100

申请日：2017-10-27

Applicant: Renesas Electronics Corporation

Inventor： Daisuke KONDO

IPC: H03K17/16 ,  H02P9/00 ,  H01L29/739 ,  H01L29/861 ,  H01L49/02 ,  H01L25/065 ,  H01L23/00 ,  H02M5/458 ,  H03K17/567 ,  H03K17/94 ,  F03D9/25

CPC classification number: H03K17/168 ,  F03D9/255 ,  H01L24/48 ,  H01L25/0655 ,  H01L28/20 ,  H01L29/7397 ,  H01L29/861 ,  H01L2224/0603 ,  H01L2224/48139 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2924/1203 ,  H01L2924/1207 ,  H01L2924/13055 ,  H01L2924/19107 ,  H01L2924/30105 ,  H02M1/088 ,  H02M3/3155 ,  H02M3/325 ,  H02M5/458 ,  H02M7/5387 ,  H02M2001/0012 ,  H02M2001/0038 ,  H02P9/008 ,  H02P2101/15 ,  H03K17/08128 ,  H03K17/163 ,  H03K17/567 ,  H03K17/74 ,  H03K17/94 ,  Y02E10/725

Abstract: The present disclosure attempts to improve performance of a semiconductor apparatus including a power transistor such as an IGBT. In a semiconductor apparatus, an IGBT module 110 includes IGBT elements SWa and SWb connected in parallel to each other, a resistor R1a connected to a gate terminal of the IGBT element SWa, and a diode D1a connected in parallel to the resistor R1a. In the diode D1a, a direction toward the gate terminal of the IGBT element SWa is a forward direction. With this configuration, it is possible to prevent gate oscillation and to improve switching characteristics.

公开(公告)号：US20180248492A1

公开(公告)日：2018-08-30

申请号：US15965178

申请日：2018-04-27

Applicant: Renesas Electronics Corporation

Inventor： Daisuke KONDO ,  Koji TATENO ,  Chang LIU ,  Nao NAGATA

IPC: H02M5/458 ,  H01L29/00 ,  H02M1/08 ,  H03K17/12 ,  H03K17/567 ,  H03K17/61 ,  H03K17/691 ,  H03K17/795

CPC classification number: H02M5/458 ,  H01L29/00 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/4238 ,  H01L29/7396 ,  H01L29/7397 ,  H02M1/08 ,  H03K17/127 ,  H03K17/168 ,  H03K17/567 ,  H03K17/61 ,  H03K17/691 ,  H03K17/7955 ,  H03K2217/0081

Abstract: A power conversion device includes a high-side transistor including an IGBT, a low-side transistor including an IGBT, and having a collector coupled to an emitter of the high-side transistor, a high-side driver configured to drive the high-side transistor; and a low-side driver configured to drive the low-side transistor, wherein each of the high-side transistor and the low-side transistor includes a first trench gate electrode arranged in an active cell region, and electrically connected to a gate, and a second trench gate electrode and a third trench gate electrode, each of which is arranged at intervals on both sides of the first trench gate electrode, and electrically connected to the emitter in the active cell region. The high-side driver includes a first pull-up transistor configured to apply a first voltage as a positive voltage to the gate, based on the emitter of the high-side transistor and a first pull-down transistor.

公开(公告)号：US20140176093A1

公开(公告)日：2014-06-26

申请号：US14064522

申请日：2013-10-28

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takahiro NOMIYAMA ,  Koji TATENO ,  Daisuke KONDO

IPC: H02M3/158

CPC classification number: H02M3/158 ,  H01L2224/0603 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H02M2001/0058 ,  H03K17/122 ,  H03K17/164 ,  H03K2217/0036 ,  H03K2217/0063 ,  H03K2217/0072 ,  Y02B70/1491

Abstract: A switching loss is reduced by reducing a deviation from the operational principle of zero-volt switching (ZVS). A semiconductor integrated circuit includes high-side switch elements Q11 and Q12, a low-side switch element Q2, and a controller CNT. A decoupling capacitance Cin is coupled between one end of a high-side element and an earth potential, and the high-side element includes the first and second transistors Q11 and Q12 coupled in parallel. In changing the high-side elements from an on-state to an off-state, CNT controls Q12 from an on-state to an off-state by delaying Q12 relative to Q11. Q11 and Q12 are divided into a plurality of parts inside a semiconductor chip Chip 1, a plurality of partial first transistors formed by dividing Q11 and a plurality of partial second transistors formed by dividing Q12 are alternately arranged in an arrangement direction of Q11 and Q12, inside the semiconductor chip Chip 1.

Abstract translation: 通过减少与零电压开关（ZVS）的工作原理的偏差来减少开关损耗。 半导体集成电路包括高侧开关元件Q11和Q12，低侧开关元件Q2和控制器CNT。 去耦电容Cin耦合在高侧元件的一端和地电位之间，高侧元件包括并联耦合的第一和第二晶体管Q11和Q12。 在将高端元件从导通状态切换到截止状态时，CNT通过相对于Q11延迟Q12，将Q12从导通状态切换到关闭状态。 Q11和Q12被分成半导体芯片芯片1内的多个部分，通过划分Q11而形成的多个局部第一晶体管和由Q12分割成的多个部分第二晶体管沿Q11和Q12的排列方向交替布置， 在半导体芯片芯片1内。