公开(公告)号：US20160020207A1

公开(公告)日：2016-01-21

申请号：US14800207

申请日：2015-07-15

Applicant: Renesas Electronics Corporation

Inventor： Hideaki Tsuchiya ,  Hiroshi Kimura ,  Takashi Ide ,  Yorinobu Kunimune

IPC: H01L27/088 ,  H01L29/20 ,  H01L23/532 ,  H01L29/417 ,  H01L29/45 ,  H01L27/06 ,  H01L23/528

CPC classification number: H01L29/7787 ,  H01L23/528 ,  H01L23/53223 ,  H01L27/0605 ,  H01L27/088 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/66462 ,  H01L29/7786 ,  H01L2924/0002 ,  H01L2924/00

Abstract: To enhance electromigration resistance of an electrode.A drain electrode is partially formed on a side surface of a drain pad. In this case, the drain electrode is integrated with the drain pad and extends from the side surface of the drain pad in a first direction (y direction). A recessed portion is located in a region overlapping with the drain electrode in a plan view. At least a part of the drain electrode is buried in the recessed portion. A side surface of the recessed portion, which faces the drain pad, enters the drain pad in the first direction (y direction).

公开(公告)号：US10074740B2

公开(公告)日：2018-09-11

申请号：US15642299

申请日：2017-07-05

Applicant: Renesas Electronics Corporation

Inventor： Hideaki Tsuchiya ,  Hiroshi Kimura ,  Takashi Ide ,  Yorinobu Kunimune

IPC: H01L29/778 ,  H01L23/528 ,  H01L23/532 ,  H01L27/088 ,  H01L29/417 ,  H01L27/06 ,  H01L29/45 ,  H01L29/66 ,  H01L29/20 ,  H01L29/40 ,  H01L29/423

CPC classification number: H01L29/7787 ,  H01L23/528 ,  H01L23/53223 ,  H01L27/0605 ,  H01L27/088 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/66462 ,  H01L29/7786 ,  H01L2924/0002 ,  H01L2924/00

Abstract: To enhance electromigration resistance of an electrode.A drain electrode is partially formed on a side surface of a drain pad. In this case, the drain electrode is integrated with the drain pad and extends from the side surface of the drain pad in a first direction (y direction). A recessed portion is located in a region overlapping with the drain electrode in a plan view. At least a part of the drain electrode is buried in the recessed portion. A side surface of the recessed portion, which faces the drain pad, enters the drain pad in the first direction (y direction).

公开(公告)号：US20170110399A1

公开(公告)日：2017-04-20

申请号：US15394752

申请日：2016-12-29

Applicant: Renesas Electronics Corporation

Inventor： Tatsuya Usami ,  Yukio Miura ,  Hideaki Tsuchiya

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/265 ,  H01L21/02 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/02074 ,  H01L21/02126 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/263 ,  H01L21/265 ,  H01L21/3105 ,  H01L21/31144 ,  H01L21/321 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76859 ,  H01L21/76879 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes an interlayer insulating film INS2, adjacent Cu wirings M1W formed in the interlayer insulating film INS2, and an insulating barrier film BR1 which is in contact with a surface of the interlayer insulating film INS2 and surfaces of the Cu wirings M1W and covers the interlayer insulating film INS2 and the Cu wirings M1W. Between the adjacent Cu wirings M1W, the interlayer insulating film INS2 has a damage layer DM1 on its surface, and has an electric field relaxation layer ER1 having a higher nitrogen concentration than a nitrogen concentration of the damage layer DM1 at a position deeper than the damage layer DM1.

公开(公告)号：US11063009B2

公开(公告)日：2021-07-13

申请号：US15888846

申请日：2018-02-05

Applicant: Renesas Electronics Corporation

Inventor： Kenji Sakata ,  Toshihiko Akiba ,  Takuo Funaya ,  Hideaki Tsuchiya ,  Yuichi Yoshida

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/31 ,  H01L23/29

Abstract: There is a need to improve reliability of the semiconductor device.
A semiconductor device includes a printed circuit board and a semiconductor chip mounted over the printed circuit board. The semiconductor chip includes a pad, an insulation film including an opening to expose part of the pad, and a pillar electrode formed over the pad exposed from the opening. The printed circuit board includes a terminal and a resist layer including an opening to expose part of the terminal. The pillar electrode of the semiconductor chip and the terminal of the printed circuit board are coupled via a solder layer. Thickness h1 of the pillar electrode is measured from the upper surface of the insulation film. Thickness h2 of the solder layer is measured from the upper surface of the resist layer. Thickness h1 is greater than or equal to a half of thickness h2 and is smaller than or equal to thickness h2.

公开(公告)号：US20170301782A1

公开(公告)日：2017-10-19

申请号：US15642299

申请日：2017-07-05

Applicant: Renesas Electronics Corporation

Inventor： Hideaki Tsuchiya ,  Hiroshi Kimura ,  Takashi Ide ,  Yorinobu Kunimune

IPC: H01L29/778 ,  H01L23/532 ,  H01L27/06 ,  H01L29/66 ,  H01L29/417 ,  H01L23/528 ,  H01L29/20 ,  H01L27/088 ,  H01L29/45 ,  H01L29/40 ,  H01L29/423

CPC classification number: H01L29/7787 ,  H01L23/528 ,  H01L23/53223 ,  H01L27/0605 ,  H01L27/088 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/66462 ,  H01L29/7786 ,  H01L2924/0002 ,  H01L2924/00

Abstract: To enhance electromigration resistance of an electrode.A drain electrode is partially formed on a side surface of a drain pad. In this case, the drain electrode is integrated with the drain pad and extends from the side surface of the drain pad in a first direction (y direction). A recessed portion is located in a region overlapping with the drain electrode in a plan view. At least a part of the drain electrode is buried in the recessed portion. A side surface of the recessed portion, which faces the drain pad, enters the drain pad in the first direction (y direction).

公开(公告)号：US20160172298A1

公开(公告)日：2016-06-16

申请号：US15047623

申请日：2016-02-18

Applicant: Renesas Electronics Corporation

Inventor： Tatsuya Usami ,  Yukio Miura ,  Hideaki Tsuchiya

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/02074 ,  H01L21/02126 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/263 ,  H01L21/265 ,  H01L21/3105 ,  H01L21/31144 ,  H01L21/321 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76859 ,  H01L21/76879 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes an interlayer insulating film INS2, adjacent Cu wirings M1W formed in the interlayer insulating film INS2, and an insulating barrier film BR1 which is in contact with a surface of the interlayer insulating film INS2 and surfaces of the Cu wirings M1W and covers the interlayer insulating film INS2 and the Cu wirings M1W. Between the adjacent Cu wirings M1W, the interlayer insulating film INS2 has a damage layer DM1 on its surface, and has an electric field relaxation layer ER1 having a higher nitrogen concentration than a nitrogen concentration of the damage layer DM1 at a position deeper than the damage layer DM1.

公开(公告)号：US09159607B2

公开(公告)日：2015-10-13

申请号：US13781496

申请日：2013-02-28

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Satoshi Uno ,  Hideaki Tsuchiya ,  Shinji Yokogawa

IPC: H01L21/00 ,  H01L21/768 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L24/81 ,  H01L21/76841 ,  H01L23/49811 ,  H01L23/49866 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05099 ,  H01L2224/05186 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13611 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14177 ,  H01L2224/16058 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/814 ,  H01L2224/81447 ,  H01L2224/81801 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/2064 ,  H01L2924/3656 ,  H01L2924/04941 ,  H01L2924/01047 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor chip SC includes an electrode pad PAD. A Cu pillar PIL is formed on the electrode pad PAD. In addition, an interconnect substrate INT includes a connection terminal TER. The connection terminal TER contains Cu. For example, the connection terminal TER is formed of Cu, and is formed, for example, in a land shape. However, the connection terminal TER may not be formed in a land shape. The Cu pillar PIL and the connection terminal TER are connected to each other through a solder layer SOL. The solder layer SOL contains Sn. A Ni layer NIL is formed on either the Cu pillar PIL or the connection terminal TER. The minimum value L of the thickness of the solder layer SOL is equal to or less than 20 μm.

Abstract translation: 半导体芯片SC包括电极焊盘PAD。 在电极焊盘PAD上形成Cu柱PIL。 此外，互连基板INT包括连接端子TER。 连接端子TER含有Cu。 例如，连接端子TER由Cu形成，例如形成为平面形状。 然而，连接端子TER可以不形成为平面形状。 Cu柱PIL和连接端子TER通过焊料层SOL彼此连接。 焊料层SOL含有Sn。 在Cu柱PIL或连接端子TER上形成Ni层NIL。 焊料层SOL的厚度的最小值L等于或小于20μm。

公开(公告)号：US09293457B2

公开(公告)日：2016-03-22

申请号：US14800207

申请日：2015-07-15

Applicant: Renesas Electronics Corporation

Inventor： Hideaki Tsuchiya ,  Hiroshi Kimura ,  Takashi Ide ,  Yorinobu Kunimune

IPC: H01L27/088 ,  H01L27/06 ,  H01L29/20 ,  H01L23/528 ,  H01L29/417 ,  H01L29/45 ,  H01L23/532

CPC classification number: H01L29/7787 ,  H01L23/528 ,  H01L23/53223 ,  H01L27/0605 ,  H01L27/088 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/66462 ,  H01L29/7786 ,  H01L2924/0002 ,  H01L2924/00

Abstract: To enhance electromigration resistance of an electrode.A drain electrode is partially formed on a side surface of a drain pad. In this case, the drain electrode is integrated with the drain pad and extends from the side surface of the drain pad in a first direction (y direction). A recessed portion is located in a region overlapping with the drain electrode in a plan view. At least a part of the drain electrode is buried in the recessed portion. A side surface of the recessed portion, which faces the drain pad, enters the drain pad in the first direction (y direction).

Abstract translation: 提高电极的电迁移率。 漏电极部分地形成在漏极焊盘的侧表面上。 在这种情况下，漏电极与漏极焊盘集成，并且在漏极焊盘的侧表面沿着第一方向（y方向）延伸。 凹部在平面图中位于与漏电极重叠的区域中。 漏电极的至少一部分被埋在凹部中。 面向排水垫的凹部的侧面在第一方向（y方向）上进入排水垫。

公开(公告)号：US20150228586A1

公开(公告)日：2015-08-13

申请号：US14381572

申请日：2013-11-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tatsuya Usami ,  Yukio Miura ,  Hideaki Tsuchiya

IPC: H01L23/532 ,  H01L21/02 ,  H01L21/263 ,  H01L21/265 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/528 ,  H01L21/02074 ,  H01L21/02126 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/263 ,  H01L21/265 ,  H01L21/3105 ,  H01L21/31144 ,  H01L21/321 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76859 ,  H01L21/76879 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes an interlayer insulating film INS2, adjacent Cu wirings M1W formed in the interlayer insulating film INS2, and an insulating barrier film BR1 which is in contact with a surface of the interlayer insulating film INS2 and surfaces of the Cu wirings M1W and covers the interlayer insulating film INS2 and the Cu wirings M1W. Between the adjacent Cu wirings M1W, the interlayer insulating film INS2 has a damage layer DM1 on its surface, and has an electric field relaxation layer ER1 having a higher nitrogen concentration than a nitrogen concentration of the damage layer DM1 at a position deeper than the damage layer DM1.

Abstract translation: 半导体器件包括层间绝缘膜INS2，形成在层间绝缘膜INS2中的相邻的Cu布线M1W和与层间绝缘膜INS2的表面接触的绝缘阻挡膜BR1和Cu布线M1W和盖的表面 层间绝缘膜INS2和Cu布线M1W。 在相邻的Cu配线M1W之间，层间绝缘膜INS2在其表面具有损伤层DM1，并且在比损伤深的位置具有比损伤层DM1的氮浓度高的氮浓度的电场缓和层ER1 层DM1。

公开(公告)号：US11923296B2

公开(公告)日：2024-03-05

申请号：US17841203

申请日：2022-06-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Naohito Suzumura ,  Kenichiro Sonoda ,  Hideaki Tsuchiya

IPC: H01L23/525

CPC classification number: H01L23/5256

Abstract: An interlayer dielectric layer covers an electric fuse element. A resistance layer made of silicon metal is arranged on the interlayer dielectric layer and directly above the electric fuse element.