公开(公告)号：US20240355381A1

公开(公告)日：2024-10-24

申请号：US18306167

申请日：2023-04-24

Applicant: QUALCOMM Incorporated

Inventor： Seohee KIM ,  Chulmin JUNG ,  Xiao CHEN ,  Hanil LEE ,  Venugopal BOYNAPALLI ,  Jung Pill KIM

IPC: G11C11/413 ,  H03K5/24 ,  H10B10/00

CPC classification number: G11C11/413 ,  H03K5/24 ,  H10B10/18

Abstract: An integrated circuit is disclosed that includes a power supply multiplexer for selecting between a first power supply voltage and a second power supply voltage to provide a selected power supply voltage to a memory. A controller includes a comparator stage having a comparator with switchable inputs so that the comparator stage may control a binary state of a first output signal responsive to whether the first power supply voltage is greater than the second power supply voltage plus a voltage offset of the comparator. Similarly, the comparator stage may control a binary state of a second output signal responsive to whether the first power supply voltage is greater than the second power supply voltage minus the voltage offset. The controller controls the selection by the power supply multiplexer responsive to the binary states of the first and second output signals.

公开(公告)号：US20180019767A1

公开(公告)日：2018-01-18

申请号：US15716451

申请日：2017-09-26

Applicant: QUALCOMM Incorporated

Inventor： Seong-Ook JUNG ,  Sara CHOI ,  Byung Kyu SONG, JR. ,  Taehui NA ,  Jisu KIM ,  Jung Pill KIM ,  Sungryul KIM ,  Taehyun KIM ,  Seung Hyuk KANG

IPC: H03M13/00 ,  H03M13/15 ,  G06F11/10

CPC classification number: H03M13/616 ,  G06F11/10 ,  G06F11/1012 ,  H03M13/152 ,  H03M13/1575 ,  H03M13/617 ,  H03M13/6502

Abstract: Error detection and correction decoding apparatus performs single error correction-double error detection (SEC-DED) or double error correction-triple error detection (DEC-TED) depending on whether the data input contains a single-bit error or a multiple-bit error, to reduce power consumption and latency in case of single-bit errors and to provide powerful error correction in case of multiple-bit errors.

公开(公告)号：US20160307645A1

公开(公告)日：2016-10-20

申请号：US14691570

申请日：2015-04-20

Applicant: Qualcomm Incorporated

Inventor： Jung Pill KIM ,  Dexter Tamio CHUN ,  Jungwon SUH ,  Deepti Vijayalakshmi SRIRAMAGIRI ,  Yanru LI ,  Mosaddiq SAIFUDDIN ,  Xiangyu DONG

IPC: G11C29/44 ,  G06F11/07 ,  G11C29/00

CPC classification number: G11C29/4401 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/079 ,  G06F11/0793 ,  G06F11/1048 ,  G11C11/401 ,  G11C29/42 ,  G11C29/76

Abstract: A memory having a redundancy area is operated in a normal mode and an error is detected. A selecting selects between in-line repair process and off-line repair. In-line repair applies a short term error correction, which remaps a fail address to a remapped memory area of the memory. An in-system repair is applied, for a one-time programmed remapping of the fail address to a redundancy area of the memory. In-system repair utilizes idle time of the memory to maintain valid memory content.

Abstract translation: 具有冗余区域的存储器在正常模式下操作并且检测到错误。 选择选择在线修复过程和离线修复。 在线修复应用短期错误纠正，其将失败地址重映射到存储器的重映射存储区域。 应用系统内修复，将故障地址的一次性重新映射重新映射到存储器的冗余区域。 系统内修复利用存储器的空闲时间来维护有效的存储器内容。

公开(公告)号：US20150228322A1

公开(公告)日：2015-08-13

申请号：US14179115

申请日：2014-02-12

Applicant: QUALCOMM Incorporated ,  Industry-Academic Cooperation Foundation, Yonsei University

Inventor： Seong-Ook JUNG ,  Taehui NA ,  Ji-su KIM ,  Jung Pill KIM ,  Seung Hyuk KANG

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C7/02 ,  G11C7/065 ,  G11C7/08 ,  G11C11/1693 ,  G11C13/004 ,  G11C2013/0054

Abstract: A resistive memory sensing method includes sensing outputs of an offset-cancelling dual stage sensing circuit (OCDS-SC) by an NMOS offset-cancelling current latched sense amplifier circuit (NOC-CLSA). The NOC-CLSA is configured with a reduced input capacitance and a reduced offset voltage. Input transistors of the NOC-CLSA are coupled between latch circuitry and ground. A first phase output of the OCDS-SC is stored by the NOC-CLSA during a pre-charge step of the NOC-CLSA operation. A second phase output of the OCDS-SC is stored by the NOC-CLSA during an offset-cancelling step of the NOC-CLSA operation. By pipelining the OCDS-SC and NOC-CLSA, a sensing delay penalty of the OCDS-SC is overcome.

Abstract translation: 电阻式存储器感测方法包括通过NMOS偏移消除电流锁存读出放大器电路（NOC-CLSA）来感测偏移消除双级感测电路（OCDS-SC）的输出。 NOC-CLSA配置有降低的输入电容和降低的失调电压。 NOC-CLSA的输入晶体管耦合在锁存电路和地之间。 在NOC-CLSA操作的预充电步骤期间，OCDS-SC的第一相输出由NOC-CLSA存储。 在NOC-CLSA操作的偏移消除步骤期间，OCDS-SC的第二相输出由NOC-CLSA存储。 通过流水线OCDS-SC和NOC-CLSA，克服了OCDS-SC的感测延迟损失。

公开(公告)号：US20150063012A1

公开(公告)日：2015-03-05

申请号：US14015845

申请日：2013-08-30

Applicant: Industry-Academic Cooperation Foundation ,  QUALCOMM Incorporated

Inventor： Seong-Ook JUNG ,  Taehui NA ,  Jisu KIM ,  Jung Pill KIM ,  Seung Hyuk KANG

IPC: G11C11/16 ,  G11C7/06

CPC classification number: G11C11/1673 ,  G11C7/06 ,  G11C7/065 ,  G11C11/1693 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2013/0057

Abstract: An offset canceling dual stage sensing method includes sensing a data value of a resistive memory data cell using a first load PMOS gate voltage generated by a reference value of a resistive memory reference cell in a first stage operation. The method also includes sensing the reference value of the resistive memory reference cell using a second load PMOS gate voltage generated by the data value of the resistive memory data cell in a second stage operation of the resistive memory sensing circuit. By adjusting the operating point of the reference cell sensing, an offset canceling dual stage sensing circuit increases the sense margin significantly compared to that of a conventional sensing circuit.

Abstract translation: 偏移消除双级感测方法包括使用在第一级操作中由电阻性存储器参考单元的参考值产生的第一负载PMOS栅极电压来感测电阻性存储器数据单元的数据值。 该方法还包括使用在电阻性存储器感测电路的第二级操作中由电阻性存储器数据单元的数据值产生的第二负载PMOS栅极电压来感测电阻性存储器参考单元的参考值。 通过调整参考单元感测的工作点，与常规感测电路相比，偏移消除双级感测电路显着增加了感测余量。

公开(公告)号：US20240221853A1

公开(公告)日：2024-07-04

申请号：US18605685

申请日：2024-03-14

Applicant: QUALCOMM Incorporated

Inventor： Rahul SAHU ,  Sharad Kumar GUPTA ,  Jung Pill KIM ,  Chulmin JUNG ,  Jais ABRAHAM

IPC: G11C29/10 ,  G11C7/06 ,  G11C7/10

CPC classification number: G11C29/10 ,  G11C7/06 ,  G11C7/106 ,  G11C7/1096

Abstract: A memory is provided in which a scan chain covers the redundancy logic for column redundancy as well as the redundancy multiplexers in each column. The redundancy logic includes a plurality of redundancy logic circuits arranged in series. Each redundancy logic circuit corresponds to a respective column in the memory. Each column is configured to route a shift-in signal through its redundancy multiplexers during a scan mode of operation.

公开(公告)号：US20170068460A1

公开(公告)日：2017-03-09

申请号：US15254986

申请日：2016-09-01

Applicant: QUALCOMM Incorporated

Inventor： Hyunsuk SHIN ,  Jung Pill KIM ,  Assaf Shacham

IPC: G06F3/06 ,  G06F12/08

CPC classification number: G06F3/0608 ,  G06F3/0611 ,  G06F3/0613 ,  G06F3/0625 ,  G06F3/0631 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0661 ,  G06F3/0665 ,  G06F3/0673 ,  G06F3/0679 ,  G06F3/0688

Abstract: Aspects disclosed in the detailed description include hardware accelerated storage compression. In one aspect, prior to writing an uncompressed data block to the storage device, a hardware compression accelerator provided in a storage controller compresses the uncompressed data blocks individually into a compressed data block and allocates the compressed data block to a storage data block in the storage device. The hardware compression accelerator then generates a modified logical block address (LBA) to link the uncompressed data block to the compressed data blocks. In another aspect, the hardware compression accelerator locates a compressed data block based on a corresponding modified LBA and decompresses the compressed data block into an uncompressed data block. By performing hardware accelerated storage compression in the storage controller, it is possible to reduce processing overhead associated with traditional software-based compression systems and improve compression control over traditional storage device driven compression systems.

Abstract translation: 在详细描述中公开的方面包括硬件加速存储压缩。 一方面，在将未压缩的数据块写入到存储装置之前，设置在存储控制器中的硬件压缩加速器将未压缩数据块分别压缩为压缩数据块，并将压缩数据块分配给存储器中的存储数据块 设备。 硬件压缩加速器然后生成修改的逻辑块地址（LBA），以将未压缩的数据块链接到压缩的数据块。 在另一方面，硬件压缩加速器基于对应的修改的LBA定位压缩数据块，并将压缩数据块解压缩为未压缩的数据块。 通过在存储控制器中执行硬件加速存储压缩，可以减少与传统的基于软件的压缩系统相关联的处理开销，并改进对传统存储设备驱动的压缩系统的压缩控制。

公开(公告)号：US20160276576A1

公开(公告)日：2016-09-22

申请号：US15170851

申请日：2016-06-01

Applicant: QUALCOMM Incorporated

Inventor： William H. XIA ,  Wenqing WU ,  Kendrick H. YUEN ,  Abhishek BANERJEE ,  Xia LI ,  Seung H. KANG ,  Jung Pill KIM

IPC: H01L43/02 ,  H01L43/08 ,  G11C11/16 ,  H01L43/12

CPC classification number: H01L43/02 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/1693 ,  H01L43/08 ,  H01L43/12

Abstract: A memory cell includes an elongated first electrode coupled to a magnetic tunnel junction (MTJ) structure and an elongated second electrode aligned with the elongated first electrode coupled to the MTJ structure. The elongated electrodes are configured to direct mutually additive portions of a switching current induced magnetic field through the MTJ. The mutually additive portions enhance switching of the MTJ in response to application of the switching current.

Abstract translation: 存储单元包括耦合到磁隧道结（MTJ）结构的细长第一电极和与耦合到MTJ结构的细长第一电极对准的细长第二电极。 细长电极被配置为引导开关电流感应磁场的相互添加部分通过MTJ。 响应于开关电流的应用，相互添加的部分增强MTJ的切换。

公开(公告)号：US20160093350A1

公开(公告)日：2016-03-31

申请号：US14499153

申请日：2014-09-27

Applicant: QUALCOMM Incorporated

Inventor： Seong-Ook JUNG ,  Taehui NA ,  Byungkyu SONG ,  Jung Pill KIM ,  Seung Hyuk KANG

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C7/062 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C11/165 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1675 ,  G11C2207/002

Abstract: Systems and methods relate to operations on a magnetoresistive random access memory (MRAM) bit cell using a circuit configured in multiple phases. In a sensing circuit phase, the circuit configured to determine a first differential voltage between a data voltage across the bit cell and a reference voltage. In a pre-amplifying phase, the circuit is configured to pre-amplify the first differential voltage to generate a pre-amplified differential voltage, which does not have offset voltages that may arise due to process variations. In a sense amplifier phase, the circuit is configured to amplify the pre-amplified differential voltage in a latch. Generation of the pre-amplified differential voltage cancels offset voltages which may arise in the latch. In a write phase, the circuit is further configured to write a write data value to the MRAM bit cell.

Abstract translation: 系统和方法涉及使用多阶段配置的电路的磁阻随机存取存储器（MRAM）位单元的操作。 在感测电路阶段中，电路被配置为确定位单元两端的数据电压与参考电压之间的第一差分电压。 在预放大阶段，电路被配置为对第一差分电压进行预放大，以产生预放大的差分电压，其不会由于工艺变化而产生偏移电压。 在读出放大器相位中，电路被配置为在锁存器中放大预放大的差分电压。 预放大的差分电压的产生可消除锁存器中可能出现的偏移电压。 在写入阶段，电路还被配置为将写数据值写入MRAM位单元。

公开(公告)号：US20150143198A1

公开(公告)日：2015-05-21

申请号：US14081645

申请日：2013-11-15

Applicant: QUALCOMM Incorporated

Inventor： Dexter CHUN ,  Jung Pill KIM ,  Hyunsuk SHIN ,  Jungwon SUH

IPC: G06F11/10 ,  G11C29/00

CPC classification number: G06F11/1072 ,  G06F11/1048 ,  G06F11/14 ,  G11C29/765

Abstract: A system for replacing a page stored in system memory when reading the page incurs a multiple-bit error. Upon reading a page in system memory for which a multiple-bit error is detected, backup data in flash memory is loaded into a redundant page in the system memory, and a re-mapper is configured so that future accesses to the page are redirected to the redundant page.

Abstract translation: 当读取页面时，用于替换存储在系统存储器中的页面的系统产生多位错误。 在读取检测到多位错误的系统存储器中的页面时，闪存中的备份数据被加载到系统存储器中的冗余页面中，并且配置重新映射器，以便将来对页面的访问被重定向到 冗余页面。