公开(公告)号：US20160093350A1

公开(公告)日：2016-03-31

申请号：US14499153

申请日：2014-09-27

Applicant: QUALCOMM Incorporated

Inventor： Seong-Ook JUNG ,  Taehui NA ,  Byungkyu SONG ,  Jung Pill KIM ,  Seung Hyuk KANG

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C7/062 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C11/165 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1675 ,  G11C2207/002

Abstract: Systems and methods relate to operations on a magnetoresistive random access memory (MRAM) bit cell using a circuit configured in multiple phases. In a sensing circuit phase, the circuit configured to determine a first differential voltage between a data voltage across the bit cell and a reference voltage. In a pre-amplifying phase, the circuit is configured to pre-amplify the first differential voltage to generate a pre-amplified differential voltage, which does not have offset voltages that may arise due to process variations. In a sense amplifier phase, the circuit is configured to amplify the pre-amplified differential voltage in a latch. Generation of the pre-amplified differential voltage cancels offset voltages which may arise in the latch. In a write phase, the circuit is further configured to write a write data value to the MRAM bit cell.

Abstract translation: 系统和方法涉及使用多阶段配置的电路的磁阻随机存取存储器（MRAM）位单元的操作。 在感测电路阶段中，电路被配置为确定位单元两端的数据电压与参考电压之间的第一差分电压。 在预放大阶段，电路被配置为对第一差分电压进行预放大，以产生预放大的差分电压，其不会由于工艺变化而产生偏移电压。 在读出放大器相位中，电路被配置为在锁存器中放大预放大的差分电压。 预放大的差分电压的产生可消除锁存器中可能出现的偏移电压。 在写入阶段，电路还被配置为将写数据值写入MRAM位单元。

公开(公告)号：US20170077963A1

公开(公告)日：2017-03-16

申请号：US14852988

申请日：2015-09-14

Applicant: QUALCOMM Incorporated ,  Industry-Academic Cooperation Foundation, Yonsei University

Inventor： Seong-Ook JUNG ,  Sara CHOI ,  Byungkyu SONG ,  Taehui NA ,  Jisu KIM ,  Jung Pill KIM ,  Sungryul KIM ,  Taehyun KIM ,  Seung Hyuk KANG

IPC: H03M13/00

CPC classification number: H03M13/616 ,  G06F11/10 ,  G06F11/1012 ,  H03M13/152 ,  H03M13/1575 ,  H03M13/617 ,  H03M13/6502

Abstract: Error detection and correction decoding apparatus performs single error correction-double error detection (SEC-DED) or double error correction-triple error detection (DEC-TED) depending on whether the data input contains a single-bit error or a multiple-bit error, to reduce power consumption and latency in case of single-bit errors and to provide powerful error correction in case of multiple-bit errors.

Abstract translation: 错误检测和校正解码装置根据数据输入是否包含单位错误或多位错误，执行单错误纠正双重错误检测（SEC-DED）或双重纠错三重错误检测（DEC-TED） ，以减少单位错误时的功耗和延迟，并在多位错误的情况下提供强大的纠错。

公开(公告)号：US20160093353A1

公开(公告)日：2016-03-31

申请号：US14499158

申请日：2014-09-27

Applicant: QUALCOMM Incorporated

Inventor： Seong-Ook JUNG ,  Taehui NA ,  Jisu KIM ,  Jung Pill KIM ,  Seung Hyuk KANG

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C7/065 ,  G11C11/1659 ,  G11C2207/002

Abstract: Systems and methods for reducing a probability of read disturbance during a read operation on a resistive memory bit cell include a dual stage sensing scheme, which is used to reduce pulse widths of sensing currents for reading the resistive memory bit cell. During a first stage of the read operation on the resistive memory bit cell, a first sensing current is passed in a first direction through the resistive memory bit cell, and during a second stage of the read operation, a second sensing current is passed in an opposite, second direction through the resistive memory bit cell. Durations of the first and second stages are each equal to half of the duration of the read operation, which reduces pulse width of the first and second sensing currents. Probability of read disturbance occurring is limited to at most one of the first or second stages.

Abstract translation: 用于在电阻式存储器位单元的读取操作期间降低读取干扰概率的系统和方法包括双级感测方案，其用于减少用于读取电阻性存储器位单元的感测电流的脉冲宽度。 在电阻式存储器位单元的读操作的第一阶段期间，第一感测电流沿第一方向通过电阻存储器位单元，并且在读操作的第二阶段期间，第二感测电流通过 相反的，第二方向通过电阻式存储器位单元。 第一级和第二级的持续时间均等于读取操作的持续时间的一半，这减少了第一和第二感测电流的脉冲宽度。 发生读取干扰的概率被限制在第一或第二阶段中的至多一个。

公开(公告)号：US20160093352A1

公开(公告)日：2016-03-31

申请号：US14499156

申请日：2014-09-27

Applicant: QUALCOMM Incorporated

Inventor： Seong-Ook JUNG ,  Taehui NA ,  Jisu KIM ,  Jung Pill KIM ,  Seung Hyuk KANG

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C7/14 ,  G11C29/021 ,  G11C29/028

Abstract: Systems and methods relate to providing a correct reference voltage for reading a resistive memory element such as a magnetoresistive random access memory (MRAM) bit cell. Two or more reference voltages are provided for each MRAM bit cell and a correct reference voltage is selected from the two or more reference voltages for reading the MRAM bit cell. The correct reference voltage meets sensing margin requirements for reading the MRAM bit cell and overcomes non-idealities and offset voltages in read circuitry for reading the MRAM bit cell. An indication of the correct reference voltage is stored in a non-volatile latch or other non-volatile programmable memory and provided to the read circuitry.

Abstract translation: 系统和方法涉及提供用于读取诸如磁阻随机存取存储器（MRAM）位单元的电阻性存储器元件的正确参考电压。 为每个MRAM位单元提供两个或更多个参考电压，并且从用于读取MRAM位单元的两个或更多个参考电压中选择正确的参考电压。 正确的参考电压满足读取MRAM位单元的感应余量要求，并克服读取MRAM位单元读取电路中的非理想和偏移电压。 正确的参考电压的指示被存储在非易失性锁存器或其它非易失性可编程存储器中并提供给读取电路。

公开(公告)号：US20160093351A1

公开(公告)日：2016-03-31

申请号：US14499155

申请日：2014-09-27

Applicant: QUALCOMM Incorporated

Inventor： Seong-Ook JUNG ,  Sara CHOI ,  Jisu KIM ,  Taehui NA ,  Jung Pill KIM ,  Seung Hyuk KANG

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C7/062 ,  G11C7/08 ,  G11C7/14 ,  G11C13/004 ,  G11C2013/0045 ,  G11C2013/0054

Abstract: Systems and methods relate to providing a constant sensing current for reading a resistive memory element. A load voltage generator provides a load voltage based on a current mirror configured to supply a constant current that is invariant with process-voltage-temperature variations. A data voltage is generated based on the generated load voltage, by passing a sensing current mirrored from the constant current, through the resistive memory element. A reference voltage is generated, also based on the generated load voltage and by passing reference current mirrored from the constant current, through reference cells. A logical value stored in the resistive memory element is determined based on a comparison of the data voltage and the reference voltage, where the determination is free from effects of process-voltage-temperature variations.

Abstract translation: 系统和方法涉及提供用于读取电阻式存储器元件的恒定感测电流。 负载电压发生器基于配置为提供与过程电压 - 温度变化不变的恒定电流的电流镜提供负载电压。 基于所产生的负载电压，通过将从恒定电流反射的感测电流通过电阻性存储元件来产生数据电压。 产生参考电压，也可以基于产生的负载电压，并通过将从恒定电流反射的参考电流通过参考单元。 存储在电阻性存储器元件中的逻辑值基于数据电压和参考电压的比较来确定，其中确定不受处理电压 - 温度变化的影响。

公开(公告)号：US20180019767A1

公开(公告)日：2018-01-18

申请号：US15716451

申请日：2017-09-26

Applicant: QUALCOMM Incorporated

Inventor： Seong-Ook JUNG ,  Sara CHOI ,  Byung Kyu SONG, JR. ,  Taehui NA ,  Jisu KIM ,  Jung Pill KIM ,  Sungryul KIM ,  Taehyun KIM ,  Seung Hyuk KANG

IPC: H03M13/00 ,  H03M13/15 ,  G06F11/10

CPC classification number: H03M13/616 ,  G06F11/10 ,  G06F11/1012 ,  H03M13/152 ,  H03M13/1575 ,  H03M13/617 ,  H03M13/6502

Abstract: Error detection and correction decoding apparatus performs single error correction-double error detection (SEC-DED) or double error correction-triple error detection (DEC-TED) depending on whether the data input contains a single-bit error or a multiple-bit error, to reduce power consumption and latency in case of single-bit errors and to provide powerful error correction in case of multiple-bit errors.

公开(公告)号：US20150228322A1

公开(公告)日：2015-08-13

申请号：US14179115

申请日：2014-02-12

Applicant: QUALCOMM Incorporated ,  Industry-Academic Cooperation Foundation, Yonsei University

Inventor： Seong-Ook JUNG ,  Taehui NA ,  Ji-su KIM ,  Jung Pill KIM ,  Seung Hyuk KANG

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C7/02 ,  G11C7/065 ,  G11C7/08 ,  G11C11/1693 ,  G11C13/004 ,  G11C2013/0054

Abstract: A resistive memory sensing method includes sensing outputs of an offset-cancelling dual stage sensing circuit (OCDS-SC) by an NMOS offset-cancelling current latched sense amplifier circuit (NOC-CLSA). The NOC-CLSA is configured with a reduced input capacitance and a reduced offset voltage. Input transistors of the NOC-CLSA are coupled between latch circuitry and ground. A first phase output of the OCDS-SC is stored by the NOC-CLSA during a pre-charge step of the NOC-CLSA operation. A second phase output of the OCDS-SC is stored by the NOC-CLSA during an offset-cancelling step of the NOC-CLSA operation. By pipelining the OCDS-SC and NOC-CLSA, a sensing delay penalty of the OCDS-SC is overcome.

Abstract translation: 电阻式存储器感测方法包括通过NMOS偏移消除电流锁存读出放大器电路（NOC-CLSA）来感测偏移消除双级感测电路（OCDS-SC）的输出。 NOC-CLSA配置有降低的输入电容和降低的失调电压。 NOC-CLSA的输入晶体管耦合在锁存电路和地之间。 在NOC-CLSA操作的预充电步骤期间，OCDS-SC的第一相输出由NOC-CLSA存储。 在NOC-CLSA操作的偏移消除步骤期间，OCDS-SC的第二相输出由NOC-CLSA存储。 通过流水线OCDS-SC和NOC-CLSA，克服了OCDS-SC的感测延迟损失。

公开(公告)号：US20150063012A1

公开(公告)日：2015-03-05

申请号：US14015845

申请日：2013-08-30

Applicant: Industry-Academic Cooperation Foundation ,  QUALCOMM Incorporated

Inventor： Seong-Ook JUNG ,  Taehui NA ,  Jisu KIM ,  Jung Pill KIM ,  Seung Hyuk KANG

IPC: G11C11/16 ,  G11C7/06

CPC classification number: G11C11/1673 ,  G11C7/06 ,  G11C7/065 ,  G11C11/1693 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2013/0057

Abstract: An offset canceling dual stage sensing method includes sensing a data value of a resistive memory data cell using a first load PMOS gate voltage generated by a reference value of a resistive memory reference cell in a first stage operation. The method also includes sensing the reference value of the resistive memory reference cell using a second load PMOS gate voltage generated by the data value of the resistive memory data cell in a second stage operation of the resistive memory sensing circuit. By adjusting the operating point of the reference cell sensing, an offset canceling dual stage sensing circuit increases the sense margin significantly compared to that of a conventional sensing circuit.

Abstract translation: 偏移消除双级感测方法包括使用在第一级操作中由电阻性存储器参考单元的参考值产生的第一负载PMOS栅极电压来感测电阻性存储器数据单元的数据值。 该方法还包括使用在电阻性存储器感测电路的第二级操作中由电阻性存储器数据单元的数据值产生的第二负载PMOS栅极电压来感测电阻性存储器参考单元的参考值。 通过调整参考单元感测的工作点，与常规感测电路相比，偏移消除双级感测电路显着增加了感测余量。