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    METHOD AND APPARATUS FOR GENERATING A REFERENCE FOR USE WITH A MAGNETIC TUNNEL JUNCTION
    1.
    发明申请
    METHOD AND APPARATUS FOR GENERATING A REFERENCE FOR USE WITH A MAGNETIC TUNNEL JUNCTION 有权
    用于产生用于具有磁性隧道结的参考的方法和装置

    公开(公告)号：US20150302912A1

    公开(公告)日：2015-10-22

    申请号：US14257794

    申请日：2014-04-21

    Applicant: QUALCOMM Incorporated

    Inventor： Sungryul KIM ,  Taehyun KIM ,  Jung Pill KIM

    IPC: G11C11/16

    CPC classification number: G11C11/1673 ,  G11C7/14 ,  G11C11/1659

    Abstract: Methods and apparatus for generating a reference for use with a magnetic tunnel junction are provided. In an example, provided is a magnetoresistive read only memory including a magnetic tunnel junction (MTJ) storage element, a sense amplifier having a first input coupled to the MTJ storage element, and a reference resistance device coupled to a second input of the sense amplifier. The reference resistance device includes a plurality of groups of at least two reference MTJ devices. Each reference MTJ device in a respective group is coupled in parallel with each other reference MTJ device in the respective group. Each group is coupled in series with the other groups. This arrangement advantageously mitigates read disturbances and reference level variations, while saving power, reducing reference resistance device area, and increasing read speed.

    Abstract translation: 提供了用于产生用于磁性隧道结的参考的方法和装置。 在一个例子中，提供了一种包括磁性隧道结（MTJ）存储元件的磁阻只读存储器，具有耦合到MTJ存储元件的第一输入的读出放大器和耦合到读出放大器的第二输入的参考电阻器件 。 参考电阻装置包括多组至少两个参考MTJ装置。 相应组中的每个参考MTJ设备与相应组中的每个其他参考MTJ设备并联耦合。 每个组与其他组串联。 这种布置有利于减轻读取干扰和参考电平变化，同时节省功率，减少参考电阻器件面积并增加读取速度。

    DYNAMIC MEMORY PROTECTION
    3.
    发明申请
    DYNAMIC MEMORY PROTECTION 审中-公开

    公开(公告)号：US20190332306A1

    公开(公告)日：2019-10-31

    申请号：US15963668

    申请日：2018-04-26

    Applicant: QUALCOMM Incorporated

    Inventor： Chando PARK ,  Wei-Chuan CHEN ,  Sungryul KIM ,  Adam Edward NEWHAM ,  Seung Hyuk KANG ,  Rashid Ahmed Akbar ATTAR

    IPC: G06F3/06 ,  G11C11/00 ,  G11C29/52 ,  A61N1/372

    Abstract: Aspects of the present disclosure relate to protecting the contents of memory in an electronic device, and in particular to systems and methods for transferring data between memories of an electronic device in the presence of strong magnetic fields. In one embodiment, a method of protecting data in a memory in an electronic device includes storing data in a first memory in the electronic device; determining, via a magnetic sensor, a strength of an ambient magnetic field; comparing the strength of the ambient magnetic field to a threshold; transferring the data in the first memory to a second memory in the electronic device upon determining that the strength of the ambient magnetic field exceeds the threshold; and transferring the data from the second memory to the first memory upon determining that the strength of the ambient magnetic field no longer exceeds the threshold.

    POWER GATING DEVICES AND METHODS
    5.
    发明申请
    POWER GATING DEVICES AND METHODS 审中-公开
    功率增益装置和方法

    公开(公告)号：US20170070225A1

    公开(公告)日：2017-03-09

    申请号：US14847387

    申请日：2015-09-08

    Applicant: QUALCOMM Incorporated

    Inventor： Jung Pill KIM ,  Sungryul KIM ,  Taehyun KIM

    IPC: H03K17/687 ,  H03K17/693

    CPC classification number: H03K17/6871 ,  H03K17/693 ,  H03K19/0016

    Abstract: A device includes a first power rail and a second power rail. A second voltage of the second power rail is derived from a first voltage of the first power rail. The device includes a power gating circuit that includes a switching device connected between the first power rail and the second power rail. The power gating circuit further includes a clamping diode connected in parallel to the switching device between the first power rail and the second power rail. The device further includes a logic circuit including a first inverter and a second inverter. The first inverter includes a first transistor and the second inverter includes a first transistor. A source/drain terminal of the first transistor of the first inverter is directly coupled to the first power rail, and a source/drain terminal of the first transistor of the second inverter is directly coupled to the second power rail.

    Abstract translation: 设备包括第一电力轨和第二电力轨。 第二电力轨的第二电压是从第一电力轨的第一电压导出的。 该装置包括电源门控电路，其包括连接在第一电力轨道和第二电力轨道之间的开关装置。 电源门控电路还包括与第一电源轨和第二电源轨之间的开关装置并联连接的钳位二极管。 该装置还包括包括第一反相器和第二反相器的逻辑电路。 第一反相器包括第一晶体管，第二反相器包括第一晶体管。 第一反相器的第一晶体管的源极/漏极端子直接耦合到第一电力轨道，并且第二反相器的第一晶体管的源极/漏极端子直接耦合到第二电力轨道。

    SYSTEM AND METHOD OF CONCURRENT READ/WRITE MAGNETO-RESISTIVE MEMORY
    7.
    发明申请
    SYSTEM AND METHOD OF CONCURRENT READ/WRITE MAGNETO-RESISTIVE MEMORY 审中-公开
    并联读/写磁阻存储器的系统和方法

    公开(公告)号：US20150310904A1

    公开(公告)日：2015-10-29

    申请号：US14263632

    申请日：2014-04-28

    Applicant: QUALCOMM Incorporated

    Inventor： Taehyun KIM ,  Jung Pill KIM ,  Sungryul KIM ,  Xiangyu DONG

    IPC: G11C11/16

    CPC classification number: G11C11/1653 ,  G11C7/1039 ,  G11C7/1042 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C2207/2209 ,  G11C2207/2281 ,  G11C2207/229

    Abstract: In a memory having a first memory cell array, a second memory cell array, an address is received on an address port. Based on the address, an internal address is transmitted, and it is latched and held for a first interval as a first array address. The first memory cell array is accessed over the first interval, based on the first array address. Another address is received at the address port, during the first interval, and another internal address is transmitted, and latched and held for a second interval that overlaps the first interval, as a second array address. The second memory cell array is accessed during the second interval, based on the second array address.

    Abstract translation: 在具有第一存储单元阵列的存储器中，第二存储单元阵列在地址端口上接收地址。 基于该地址，发送内部地址，并将其锁存并保持第一间隔作为第一阵列地址。 基于第一个阵列地址，第一个存储单元阵列在第一个时间间隔内被访问。 在第一间隔期间在地址端口处接收另一地址，并且发送另一内部地址，并将其锁存并保持与第一间隔重叠的第二间隔作为第二阵列地址。 基于第二阵列地址在第二间隔期间访问第二存储单元阵列。

    REAL TIME CORRECTION OF BIT FAILURE IN RESISTIVE MEMORY
    9.
    发明申请
    REAL TIME CORRECTION OF BIT FAILURE IN RESISTIVE MEMORY 有权
    电阻存储器中位故障的实时校正

    公开(公告)号：US20150194201A1

    公开(公告)日：2015-07-09

    申请号：US14150559

    申请日：2014-01-08

    Applicant: QUALCOMM Incorporated

    Inventor： Taehyun KIM ,  Sungryul KIM ,  Jung Pill KIM

    IPC: G11C11/16 ,  G06F11/10 ,  H03M13/05

    CPC classification number: G06F11/0766 ,  G06F11/1008 ,  G11C29/808 ,  G11C29/814 ,  G11C2029/0411 ,  H03M13/05

    Abstract: Systems and methods for correcting bit failures in a resistive memory device include dividing the memory device into a first memory bank and a second memory bank. A first single bit repair (SBR) array is stored in the second memory bank, wherein the first SBR array is configured to store a first indication of a failure in a first failed bit in a first row of the first memory bank. The first memory bank and the first SBR array are configured to be accessed in parallel during a memory access operation. Similarly, a second SBR array stored in the first memory bank can store indications of failures of bits in the second memory bank, wherein the second SBR array and the second memory bank can be accessed in parallel. Thus, bit failures in the first and second memory banks can be corrected in real time.

    Abstract translation: 用于校正电阻存储器件中的位故障的系统和方法包括将存储器件划分成第一存储体和第二存储体。 第一单位修复（SBR）阵列存储在第二存储体中，其中第一SBR阵列被配置为在第一存储体的第一行中的第一故障位中存储故障的第一指示。 第一存储器组和第一SBR阵列被配置为在存储器访问操作期间并行访问。 类似地，存储在第一存储体中的第二SBR阵列可以存储位在第二存储体中的故障的指示，其中可以并行地访问第二SBR阵列和第二存储体。 因此，可以实时地校正第一和第二存储体中的位故障。

    WRITE PULSE WIDTH SCHEME IN A RESISTIVE MEMORY
    10.
    发明申请
    WRITE PULSE WIDTH SCHEME IN A RESISTIVE MEMORY 有权
    写脉冲宽度方案在电阻记忆中

    公开(公告)号：US20150117086A1

    公开(公告)日：2015-04-30

    申请号：US14064959

    申请日：2013-10-28

    Applicant: QUALCOMM Incorporated

    Inventor： Taehyun KIM ,  Jung Pill KIM ,  Sungryul KIM

    IPC: G11C11/16 ,  G11C29/54

    CPC classification number: G11C11/1675 ,  G11C11/1677 ,  G11C13/0002 ,  G11C13/0069 ,  G11C29/021 ,  G11C29/023 ,  G11C29/028 ,  G11C29/24 ,  G11C2013/0083 ,  G11C2013/0092

    Abstract: A resistive memory array includes a controller, a test reset driver coupled to the controller, a test write driver also coupled to the controller, and a test read sense amplifier also coupled to the controller. The resistive memory array also includes a set of test resistive memory elements representing a resistive memory macro. The test resistive memory elements are coupled to the test reset driver, the test write driver and the test read sense amplifier. A change in the state of one of the test resistive memory elements represents a change in the state of a set of corresponding elements in the resistive memory macro.

    Abstract translation: 电阻性存储器阵列包括控制器，耦合到控制器的测试复位驱动器，还耦合到控制器的测试写入驱动器，以及还耦合到控制器的测试读取读出放大器。 电阻存储器阵列还包括表示电阻存储器宏的一组测试电阻存储器元件。 测试电阻存储元件耦合到测试复位驱动器，测试写驱动器和测试读读放大器。 一个测试电阻存储器元件的状态的变化表示电阻存储器宏中一组相应元件的状态的变化。

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