公开(公告)号：US20230170000A1

公开(公告)日：2023-06-01

申请号：US17456773

申请日：2021-11-29

Applicant: QUALCOMM Incorporated

Inventor： Arun Babu PALLERLA ,  Anil Chowdary KOTA ,  Changho JUNG ,  Chulmin JUNG

IPC: G11C7/10 ,  G11C7/12 ,  G11C5/14

CPC classification number: G11C7/106 ,  G11C7/1087 ,  G11C7/1063 ,  G11C7/12 ,  G11C5/14

Abstract: Various implementations provide systems and methods for reading data from memory bit cells. An example implementation includes a read circuit that provides a single-ended output from a sensing stage. The single-ended output is received by a reset-set (RS) latch, which also receives a virtual bit line signal. The single-ended output and the virtual bit line signal provide complementary inputs to the RS latch, and the RS latch stores a sensed bit, and the sensed bit may be driven onto a data bus.

公开(公告)号：US20230005546A1

公开(公告)日：2023-01-05

申请号：US17367248

申请日：2021-07-02

Applicant: QUALCOMM Incorporated

Inventor： Xiao CHEN ,  Chen-ju HSIEH ,  Sung SON ,  Chulmin JUNG

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/24 ,  G11C16/08 ,  G11C16/04 ,  G11C17/12

Abstract: A drain programmed read-only memory includes a diffusion region that spans a width of a bitcell and forms a drain of a first transistor and a second transistor. A bit line lead in a metal layer adjacent the diffusion region extends across the width of the bitcell. A first via extends from an upper half of the bit line lead and couples to a drain of the first transistor. Similarly, a second via extends from a lower half of the bit line and couples to a drain of the second transistor.

公开(公告)号：US20200335151A1

公开(公告)日：2020-10-22

申请号：US16849616

申请日：2020-04-15

Applicant: QUALCOMM Incorporated

Inventor： Chulmin JUNG ,  Keejong KIM ,  Changho JUNG ,  Venugopal BOYNAPALLI

IPC: G11C11/4091 ,  G11C11/4094 ,  G11C11/4099 ,  G11C11/4074 ,  G11C11/408

Abstract: A charge-transfer transistor couples between a bit line and a sense node for a sense amplifier. During a read operation, a charge-transfer driver drives a gate voltage of the charge-transfer transistor to control whether the charge-transfer transistor conducts during a charge-transfer period. Prior to the charge-transfer period, a bitcell is coupled to the bit line to drive a bitcell-effected voltage on to the bit line. The charge-transfer driver drives the gate voltage such that the charge-transfer transistor only conducts when the bitcell-effected voltage equals a pre-charge voltage for the bit line.

公开(公告)号：US20250022494A1

公开(公告)日：2025-01-16

申请号：US18349918

申请日：2023-07-10

Applicant: QUALCOMM Incorporated

Inventor： Hochul LEE ,  Anil Chowdary KOTA ,  Dhvani SHETH ,  Bin LIANG ,  Chulmin JUNG

IPC: G11C7/10 ,  G11C7/08

Abstract: A memory is provided with a pair of banks including a first bank of bitcells and a second bank of bitcells. An I/O circuit for the pair of banks includes a shared write path configured to couple a write driver input signal to the first bank of bitcells responsive to an assertion of a write enable signal for the first bank of bitcells and to couple the write driver input signal to the second bank of bitcells responsive to an assertion of a write enable signal for the second bank of bitcells. The I/O circuit also includes a shared read path configured to couple a data bit output signal from the first bank of bitcells to a sense amplifier responsive to a de-assertion of the write enable signal for the first bank of bitcells and to couple a data bit output signal from the second bank of bitcells to the sense amplifier responsive to a de-assertion of the write enable signal for the second bank of bitcells. The shared read and write paths are further configured to operate simultaneously so that a write operation to one of the banks may occur while a read operation occurs to another one of the banks.

公开(公告)号：US20240395320A1

公开(公告)日：2024-11-28

申请号：US18796143

申请日：2024-08-06

Applicant: QUALCOMM Incorporated

Inventor： Dhvani SHETH ,  Hochul LEE ,  Anil Chowdary KOTA ,  Chulmin JUNG

IPC: G11C11/419 ,  G11C11/418

Abstract: A memory is provided with a plurality of column groups and two redundant column groups. If there are two defective columns in the plurality of column groups, the plurality of column groups may be divided into a no-shift region, a one-shift region, and a two-shift region. The memory includes a plurality of input/output circuits corresponding to the plurality of column groups. Each input/output circuit may provide a data input signal during a write operation and receive a data output signal during a read operation. Each input/output circuit also includes a switch matrix. In the no-shift region, the switch matrix couples the input/output circuit to a core in the corresponding column group. In the one-shift region, the switch matrix couples the input/output circuit to a core in a subsequent column group. In the two-shift region, the switch matrix couples the input/output circuit to a core in a next-to-subsequent column group.

公开(公告)号：US20240221853A1

公开(公告)日：2024-07-04

申请号：US18605685

申请日：2024-03-14

Applicant: QUALCOMM Incorporated

Inventor： Rahul SAHU ,  Sharad Kumar GUPTA ,  Jung Pill KIM ,  Chulmin JUNG ,  Jais ABRAHAM

IPC: G11C29/10 ,  G11C7/06 ,  G11C7/10

CPC classification number: G11C29/10 ,  G11C7/06 ,  G11C7/106 ,  G11C7/1096

Abstract: A memory is provided in which a scan chain covers the redundancy logic for column redundancy as well as the redundancy multiplexers in each column. The redundancy logic includes a plurality of redundancy logic circuits arranged in series. Each redundancy logic circuit corresponds to a respective column in the memory. Each column is configured to route a shift-in signal through its redundancy multiplexers during a scan mode of operation.

公开(公告)号：US20230317150A1

公开(公告)日：2023-10-05

申请号：US17657231

申请日：2022-03-30

Applicant: QUALCOMM Incorporated

Inventor： Chulmin JUNG ,  Xiao CHEN ,  Chi-Jui CHEN ,  Anil Chowdary KOTA ,  Dhvani SHETH

IPC: G11C11/419 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C11/412

Abstract: A memory is provided that includes bitcell VDD boosting to increase a read margin. In some implementations, the positive boost for the bitcell VDD may be provided by a capacitor that is also used for negative boosting of a write driver.

公开(公告)号：US20180166129A1

公开(公告)日：2018-06-14

申请号：US15379285

申请日：2016-12-14

Applicant: QUALCOMM Incorporated

Inventor： Darshit MEHTA ,  Chulmin JUNG ,  Po-Hung CHEN

IPC: G11C11/419 ,  G06F3/06

CPC classification number: G11C11/419 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G11C7/1096 ,  G11C2207/002

Abstract: The apparatus provided may be a memory circuit. The memory circuit includes a memory cell. The memory cell has a bitline. The memory circuit also includes a write driver. The write driver is configured to drive the bitline to write a bit to the memory cell during a write operation. The write driver is also configured to float the bitline to mask the bit during a read operation. The write driver may use NMOS pullup transistors.

公开(公告)号：US20240257868A1

公开(公告)日：2024-08-01

申请号：US18104167

申请日：2023-01-31

Applicant: QUALCOMM Incorporated

Inventor： Chulmin JUNG ,  David LI ,  Po-Hung CHEN ,  Ayan PAUL ,  Derek YANG ,  Chun-Yen LIN

IPC: G11C11/419

CPC classification number: G11C11/419

Abstract: A memory is provided with a pseudo-differential sense amplifier for single-endedly sensing a first read bit line from a first bank of bitcells. The sense amplifier compares a voltage of the first read bit line to a voltage of a pre-charged second read bit line from a second bank of bitcells to make a bit decision for a read operation through the first read bit line to the first bank of bitcells.

公开(公告)号：US20230005556A1

公开(公告)日：2023-01-05

申请号：US17364738

申请日：2021-06-30

Applicant: QUALCOMM Incorporated

Inventor： Rahul SAHU ,  Sharad Kumar GUPTA ,  Jung Pill KIM ,  Chulmin JUNG ,  Jais ABRAHAM

IPC: G11C29/10 ,  G11C7/06 ,  G11C7/10

Abstract: A memory is provided in which a scan chain covers the redundancy logic for column redundancy as well as the redundancy multiplexers in each column. The redundancy logic includes a plurality of redundancy logic circuits arranged in series. Each redundancy logic circuit corresponds to a respective column in the memory. Each column is configured to route a shift-in signal through its redundancy multiplexers during a scan mode of operation.