公开(公告)号：US20220068360A1

公开(公告)日：2022-03-03

申请号：US17002082

申请日：2020-08-25

Applicant: QUALCOMM Incorporated

Inventor： Arun Babu PALLERLA ,  Changho JUNG ,  Sung SON ,  Jason CHENG ,  Yandong GAO ,  Chulmin JUNG ,  Venugopal BOYNAPALLI

IPC: G11C11/4096 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4074 ,  G11C5/02

Abstract: A bitcell architecture for a pseudo-triple-port memory is provided that includes a a bitcell arranged on a semiconductor substrate, the bitcell defining a bitcell width and a bitcell height and including a first access transistor and a second access transistor. A first metal layer adjacent the semiconductor substrate is patterned to form a pair of local bit lines arranged within the bitcell width. The pair of local bit lines includes a local bit line coupled to a terminal of the first access transistor and includes a complement local bit line coupled to a terminal of the second access transistor.

公开(公告)号：US20230005546A1

公开(公告)日：2023-01-05

申请号：US17367248

申请日：2021-07-02

Applicant: QUALCOMM Incorporated

Inventor： Xiao CHEN ,  Chen-ju HSIEH ,  Sung SON ,  Chulmin JUNG

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/24 ,  G11C16/08 ,  G11C16/04 ,  G11C17/12

Abstract: A drain programmed read-only memory includes a diffusion region that spans a width of a bitcell and forms a drain of a first transistor and a second transistor. A bit line lead in a metal layer adjacent the diffusion region extends across the width of the bitcell. A first via extends from an upper half of the bit line lead and couples to a drain of the first transistor. Similarly, a second via extends from a lower half of the bit line and couples to a drain of the second transistor.

公开(公告)号：US20220208232A1

公开(公告)日：2022-06-30

申请号：US17136616

申请日：2020-12-29

Applicant: QUALCOMM Incorporated

Inventor： David LI ,  Rahul BIRADAR ,  Biju MANAKKAM VEETIL ,  Po-Hung CHEN ,  Ayan PAUL ,  Sung SON ,  Shivendra KUSHWAHA ,  Ravindra Reddy CHEKKERA ,  Derek YANG

IPC: G11C5/02 ,  G11C7/10 ,  G11C7/06 ,  G11C8/08 ,  G11C8/10

Abstract: A semiconductor device includes: a memory circuit having a plurality of quadrants arranged at corners of the memory circuit and surrounding a bank control component; wherein a first quadrant of the plurality of quadrants includes a first bit cell core and a first set of input output circuits configured to access the first bit cell core, the first quadrant defined by a rectangular boundary that encloses portions of two perpendicular edges of the memory circuit; wherein a second quadrant of the plurality of quadrants includes a second bit cell core and a second set of input output circuits configured to access the second bit cell core, the second quadrant being adjacent the first quadrant, wherein a border between the first quadrant and the second quadrant defines a first axis about which the first quadrant and the second quadrant are symmetrical.

公开(公告)号：US20240389292A1

公开(公告)日：2024-11-21

申请号：US18318599

申请日：2023-05-16

Applicant: QUALCOMM Incorporated

Inventor： Sunil SHARMA ,  Arun Babu PALLERLA ,  Sung SON

IPC: H10B10/00

Abstract: A memory includes a bitcell on a substrate, having a bitcell width and a bitcell height and a first access transistor and a second access transistor. The memory includes a first metal layer patterned to form a first pair of wordlines, including a first wordline coupled to a gate of the first access transistor and a second wordline coupled to a gate of the second access transistor. The memory includes a second metal layer patterned to form a pair of second metal layer islands. The pair of second metal layer islands include a first island coupled to the first wordline and a second island coupled to the second wordline. The memory includes a third metal layer patterned to form a pair of third metal layer interconnects, including a first interconnect coupled to the first island and a second interconnect coupled to the second island.

公开(公告)号：US20230178118A1

公开(公告)日：2023-06-08

申请号：US18163146

申请日：2023-02-01

Applicant: QUALCOMM Incorporated

Inventor： David LI ,  Rahul BIRADAR ,  Biju MANAKKAM VEETIL ,  Po-Hung CHEN ,  Ayan PAUL ,  Sung SON ,  Shivendra KUSHWAHA ,  Ravindra Reddy CHEKKERA ,  Derek YANG

IPC: G11C5/02 ,  G11C7/06 ,  G11C7/10 ,  G11C8/08 ,  G11C8/10

CPC classification number: G11C5/025 ,  G11C7/06 ,  G11C7/1069 ,  G11C7/1096 ,  G11C8/08 ,  G11C8/10

Abstract: A semiconductor device includes: a memory circuit having a plurality of quadrants arranged at corners of the memory circuit and surrounding a bank control component; wherein a first quadrant of the plurality of quadrants includes a first bit cell core and a first set of input output circuits configured to access the first bit cell core, the first quadrant defined by a rectangular boundary that encloses portions of two perpendicular edges of the memory circuit; wherein a second quadrant of the plurality of quadrants includes a second bit cell core and a second set of input output circuits configured to access the second bit cell core, the second quadrant being adjacent the first quadrant, wherein a border between the first quadrant and the second quadrant defines a first axis about which the first quadrant and the second quadrant are symmetrical.

公开(公告)号：US20220068371A1

公开(公告)日：2022-03-03

申请号：US17001993

申请日：2020-08-25

Applicant: QUALCOMM Incorporated

Inventor： Arun Babu PALLERLA ,  Changho JUNG ,  Sung SON

IPC: G11C11/419

Abstract: A pseudo-triple-port memory is provided that includes a plurality of pseudo-triple-port bitcells, each pseudo-triple-port first bitcell having a first read port including a first word line coupled to a first bit line through a first access transistor, a second read port including a second word line coupled to a second bit line through a second access transistor, and a write port including both the word lines, both the bit lines, and the pair of access transistors.