公开(公告)号：US20230005546A1

公开(公告)日：2023-01-05

申请号：US17367248

申请日：2021-07-02

Applicant: QUALCOMM Incorporated

Inventor： Xiao CHEN ,  Chen-ju HSIEH ,  Sung SON ,  Chulmin JUNG

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/24 ,  G11C16/08 ,  G11C16/04 ,  G11C17/12

Abstract: A drain programmed read-only memory includes a diffusion region that spans a width of a bitcell and forms a drain of a first transistor and a second transistor. A bit line lead in a metal layer adjacent the diffusion region extends across the width of the bitcell. A first via extends from an upper half of the bit line lead and couples to a drain of the first transistor. Similarly, a second via extends from a lower half of the bit line and couples to a drain of the second transistor.

公开(公告)号：US20230317150A1

公开(公告)日：2023-10-05

申请号：US17657231

申请日：2022-03-30

Applicant: QUALCOMM Incorporated

Inventor： Chulmin JUNG ,  Xiao CHEN ,  Chi-Jui CHEN ,  Anil Chowdary KOTA ,  Dhvani SHETH

IPC: G11C11/419 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C11/412

Abstract: A memory is provided that includes bitcell VDD boosting to increase a read margin. In some implementations, the positive boost for the bitcell VDD may be provided by a capacitor that is also used for negative boosting of a write driver.

公开(公告)号：US20250095698A1

公开(公告)日：2025-03-20

申请号：US18469989

申请日：2023-09-19

Applicant: QUALCOMM Incorporated

Inventor： Sonia GHOSH ,  Xiao CHEN ,  Chi-Jui CHEN

IPC: G11C7/10 ,  G11C7/06 ,  G11C7/12

Abstract: A random-access memory has its bitcells arranged into a first pair of banks and a second pair of banks. The first pair of banks and second pair of banks are separated by a central controller that contains sense amplifiers and write drivers for the first pair of banks and for the second pair of banks.

公开(公告)号：US20240429908A1

公开(公告)日：2024-12-26

申请号：US18340449

申请日：2023-06-23

Applicant: QUALCOMM Incorporated

Inventor： Harshat PANT ,  Hanil LEE ,  Shih-Hsin Jason HU ,  Chulmin JUNG ,  Xiao CHEN ,  Christol BARNES

IPC: H03K17/00 ,  G05F1/46

Abstract: A system includes a comparator having a first input, a second input, and an output. The system also includes a first voltage divider having an input and an output, wherein the input of the first voltage divider is coupled to a first power rail, and the output of the first voltage divider is coupled to the first input of the comparator. The system also includes a second voltage divider having an input and an output, wherein the input of the second voltage divider is coupled to a second power rail, and the output of the second voltage divider is coupled to the second input of the comparator. The system further includes a power multiplexer coupled to the first power rail, the second power rail, and a first circuit, and a control circuit coupled to the output of the comparator and the power multiplexer.

公开(公告)号：US20240428831A1

公开(公告)日：2024-12-26

申请号：US18340807

申请日：2023-06-23

Applicant: QUALCOMM Incorporated

Inventor： Chi-Jui CHEN ,  Xiao CHEN ,  Sonia GHOSH ,  Hochul LEE ,  Anil Chowdary KOTA ,  Giby SAMSON

IPC: G11C5/14 ,  G11C11/417

Abstract: A circuit is provided with a selectively diode-connected head switch transistor. During a light-sleep mode, the head switch transistor is diode connected so that a power supply voltage passing through the diode-connected head switch transistor is reduced by a transistor threshold voltage drop. During an active mode, the diode connection is opened so that the head switch transistor passes a power supply voltage with virtually no voltage drop.

公开(公告)号：US20240355381A1

公开(公告)日：2024-10-24

申请号：US18306167

申请日：2023-04-24

Applicant: QUALCOMM Incorporated

Inventor： Seohee KIM ,  Chulmin JUNG ,  Xiao CHEN ,  Hanil LEE ,  Venugopal BOYNAPALLI ,  Jung Pill KIM

IPC: G11C11/413 ,  H03K5/24 ,  H10B10/00

CPC classification number: G11C11/413 ,  H03K5/24 ,  H10B10/18

Abstract: An integrated circuit is disclosed that includes a power supply multiplexer for selecting between a first power supply voltage and a second power supply voltage to provide a selected power supply voltage to a memory. A controller includes a comparator stage having a comparator with switchable inputs so that the comparator stage may control a binary state of a first output signal responsive to whether the first power supply voltage is greater than the second power supply voltage plus a voltage offset of the comparator. Similarly, the comparator stage may control a binary state of a second output signal responsive to whether the first power supply voltage is greater than the second power supply voltage minus the voltage offset. The controller controls the selection by the power supply multiplexer responsive to the binary states of the first and second output signals.