公开(公告)号：US20170257079A1

公开(公告)日：2017-09-07

申请号：US15058001

申请日：2016-03-01

Applicant: QUALCOMM Incorporated

Inventor： Palkesh JAIN ,  Manoj MEHROTRA ,  Yuancheng Chris PAN ,  Shih-Hsin Jason HU

IPC: H03K3/011 ,  G06F1/32

CPC classification number: H03K3/011 ,  G06F1/206 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3296 ,  H03K19/0016 ,  Y02D10/16 ,  Y02D10/171 ,  Y02D10/172

Abstract: Apparatuses and methods to adjust voltage for thermal mitigation are provided. The apparatus includes a circuit, a plurality of switches configured to provide power of a power domain to the circuit, a plurality of thermal sensors disposed at different locations about the circuit and configured to detect temperatures at the different locations, and a control circuit configured to determine that one of the detected temperatures at one of the locations exceeds a temperature threshold, and in response, adjust one or more of the plurality of switches in proximity with the one location to reduce power provided to the circuit. The method includes providing power of a power domain through a plurality of switches, detecting a temperature at a location exceeding a temperature threshold, and adjusting the plurality of switches in proximity with the location to reduce the power provided, in response to the detecting the temperature exceeding the temperature threshold.

公开(公告)号：US20210357502A1

公开(公告)日：2021-11-18

申请号：US16874538

申请日：2020-05-14

Applicant: QUALCOMM Incorporated

Inventor： Bharat Kumar RANGARAJAN ,  Dipti Ranjan PAL ,  Keith Alan BOWMAN ,  Srinivas TURAGA ,  Ateesh Deepankar DE ,  Shih-Hsin Jason HU ,  Chandan AGARWALLA

IPC: G06F21/55 ,  G06F1/26

Abstract: A method to prevent a malicious attack on CPU subsystem (CPUSS) hardware is described. The method includes auto-calibrating tunable delay elements of a dynamic variation monitor (DVM) using an auto-calibration value computed in response to each detected change of a clock frequency (Fclk)/supply voltage (Vdd) of the CPUSS hardware. The method also includes comparing the auto-calibration value with a threshold reference calibration value to determine whether the malicious attack is detected. The method further includes forcing a safe clock frequency (Fclk)/safe supply voltage (Vdd) to the CPUSS hardware when the malicious attack is detected.

公开(公告)号：US20180004689A1

公开(公告)日：2018-01-04

申请号：US15197524

申请日：2016-06-29

Applicant: QUALCOMM Incorporated

Inventor： Percy Tehmul MARFATIA ,  Rajagopal NARAYANAN ,  Shih-Hsin Jason HU ,  Nan CHEN

IPC: G06F13/16 ,  G11C7/22 ,  G11C7/10 ,  G11C11/417 ,  G11C7/04

CPC classification number: G06F13/1689 ,  G06F1/3225 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3296 ,  G11C5/14 ,  G11C7/04 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/227 ,  G11C11/417

Abstract: An apparatus includes a memory, a timing circuit configured to emulate a first operation of the memory to activate a second operation of the memory, a sensor configured to emulate a portion of the timing circuit, and a controller configured to adjust an operating parameter of the memory based on the sensor emulating the portion of the timing circuit. A method is presented. The method includes at least operating a timing circuit to emulate a first operation of the memory, activating a second operation of the memory based on the emulating the first operation of the memory, emulating, by a sensor, a portion of the timing circuit. Another apparatus is presented. The apparatus includes at least a memory, a timing circuit, and means for tracking a performance of the memory based on the timing circuit tracking a memory operation.

公开(公告)号：US20240429908A1

公开(公告)日：2024-12-26

申请号：US18340449

申请日：2023-06-23

Applicant: QUALCOMM Incorporated

Inventor： Harshat PANT ,  Hanil LEE ,  Shih-Hsin Jason HU ,  Chulmin JUNG ,  Xiao CHEN ,  Christol BARNES

IPC: H03K17/00 ,  G05F1/46

Abstract: A system includes a comparator having a first input, a second input, and an output. The system also includes a first voltage divider having an input and an output, wherein the input of the first voltage divider is coupled to a first power rail, and the output of the first voltage divider is coupled to the first input of the comparator. The system also includes a second voltage divider having an input and an output, wherein the input of the second voltage divider is coupled to a second power rail, and the output of the second voltage divider is coupled to the second input of the comparator. The system further includes a power multiplexer coupled to the first power rail, the second power rail, and a first circuit, and a control circuit coupled to the output of the comparator and the power multiplexer.

公开(公告)号：US20230421156A1

公开(公告)日：2023-12-28

申请号：US17849469

申请日：2022-06-24

Applicant: QUALCOMM Incorporated

Inventor： Basma HAJRI ,  Harshat PANT ,  Chirag AGRAWAL ,  Shih-Hsin Jason HU

IPC: H03K19/0948 ,  H03K5/01 ,  H03K19/20

CPC classification number: H03K19/0948 ,  H03K5/01 ,  H03K19/20 ,  H03K2005/00013

Abstract: An aspect relates to a glitch absorbing buffer (GABUF) including: a delay element configured to delay an input signal by a delay to generate a delayed input signal; and a logic circuit, responsive to the input signal, the delayed input signal, and an output signal, configured to propagate a pulse in the input signal to the output signal if a width of the pulse is greater than the delay, and suppress the propagating of the pulse to the output signal if the width of the pulse is less than the delay.

公开(公告)号：US20200264229A1

公开(公告)日：2020-08-20

申请号：US16277543

申请日：2019-02-15

Applicant: QUALCOMM Incorporated

Inventor： Uttkarsh WARDHAN ,  Madan M. KRISHNAPPA ,  Shih-Hsin Jason HU ,  Min CHEN

IPC: G01R31/28 ,  G01R31/00 ,  H03K3/03

Abstract: Aspects of the present disclosure provide techniques for predicting a failure of an integrated circuit, which may include receiving first aging sensor data during an idle state of the integrated circuit; determining a voltage compensation value based on the first aging sensor data; comparing a new voltage value based on the voltage compensation value to a threshold operating voltage; determining the new operating voltage value exceeds the threshold operating voltage; determining a warning state for the integrated circuit; receiving second aging sensor data during the idle state of the integrated circuit; receiving stored aging sensor data from an aging sensor data repository; comparing the second aging sensor data to the stored aging sensor data; determining that the second aging sensor data is inconsistent with the stored aging sensor data; and determining a danger state for the integrated circuit.

公开(公告)号：US20160091939A1

公开(公告)日：2016-03-31

申请号：US14497258

申请日：2014-09-25

Applicant: QUALCOMM Incorporated

Inventor： Matthew Levi SEVERSON ,  Shih-Hsin Jason HU ,  Dipti Ranjan PAL ,  Madan KRISHNAPPA ,  Jeffrey GEMAR ,  Noman AHMED ,  Mohammad TAMJIDI ,  Mark KEMPFERT

IPC: G06F1/26

CPC classification number: G06F1/26 ,  G06F1/32 ,  G06F1/3287 ,  G06F9/4405 ,  Y02D10/171

Abstract: A method for operating an electronic apparatus is provided. The method includes receiving a token, activating a power switch for powering up a core in response to the receiving the token, and outputting the token based on a state of powering up the core. The outputting of the received token is delayed until the state of powering up the core is reached. In one aspect, an electronic apparatus includes a power switch configured to power up to a core is provided. A power-switch control circuit is configured to receive a token, activate the power switch for powering up the core in response to receiving the token, output the received token based on a state of powering up the core. The outputting of the received token is delayed until the state of powering up the core is reached. A plurality of the power-switch control circuits is configured as a ring.

Abstract translation: 提供一种操作电子设备的方法。 该方法包括接收令牌，激活用于响应于接收到令牌的核心的电源开关，以及基于为核心加电的状态来输出令牌。 接收的令牌的输出被延迟直到达到核心的加电状态。 在一个方面，一种电子设备包括配置成提供电源至核心的电源开关。 功率开关控制电路被配置为接收令牌，激活电源开关以响应于接收到令牌来加电核心，基于为核心加电的状态输出接收到的令牌。 接收的令牌的输出被延迟直到达到核心的加电状态。 多个电源开关控制电路被配置为环。