公开(公告)号：US20180012649A1

公开(公告)日：2018-01-11

申请号：US15206018

申请日：2016-07-08

Applicant: QUALCOMM Incorporated

Inventor： Sonia GHOSH ,  Changho JUNG

IPC: G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C7/08 ,  G11C7/22 ,  G11C7/227 ,  G11C11/418

Abstract: A memory is presented. The memory includes a plurality of memory cells, a wordline coupled to the plurality of memory cells, a sense amplifier coupled to one of the plurality of memory cells, and a timing circuit configured to enable the sense amplifier. The timing circuit includes a delay stage and a dummy wordline. The dummy wordline is configured to emulate at least one portion of the wordline. An apparatus is presented. The apparatus include a first memory having a first wordline coupled to a first number of memory cells. A second memory having a second wordline coupled to a second number of memory cells. Each of the first memory and the second memory includes a timing circuit to enable a memory operation. The timing circuit includes a delay stage corresponding to loading of a third number of memory cells. The third number is different from the first number.

公开(公告)号：US20250095698A1

公开(公告)日：2025-03-20

申请号：US18469989

申请日：2023-09-19

Applicant: QUALCOMM Incorporated

Inventor： Sonia GHOSH ,  Xiao CHEN ,  Chi-Jui CHEN

IPC: G11C7/10 ,  G11C7/06 ,  G11C7/12

Abstract: A random-access memory has its bitcells arranged into a first pair of banks and a second pair of banks. The first pair of banks and second pair of banks are separated by a central controller that contains sense amplifiers and write drivers for the first pair of banks and for the second pair of banks.

公开(公告)号：US20240428831A1

公开(公告)日：2024-12-26

申请号：US18340807

申请日：2023-06-23

Applicant: QUALCOMM Incorporated

Inventor： Chi-Jui CHEN ,  Xiao CHEN ,  Sonia GHOSH ,  Hochul LEE ,  Anil Chowdary KOTA ,  Giby SAMSON

IPC: G11C5/14 ,  G11C11/417

Abstract: A circuit is provided with a selectively diode-connected head switch transistor. During a light-sleep mode, the head switch transistor is diode connected so that a power supply voltage passing through the diode-connected head switch transistor is reduced by a transistor threshold voltage drop. During an active mode, the diode connection is opened so that the head switch transistor passes a power supply voltage with virtually no voltage drop.

公开(公告)号：US20210255243A1

公开(公告)日：2021-08-19

申请号：US16794105

申请日：2020-02-18

Applicant: QUALCOMM Incorporated

Inventor： Sonia GHOSH ,  Changho JUNG ,  Chulmin JUNG

IPC: G01R31/3181 ,  G01J1/18 ,  G01R31/317

Abstract: According to certain aspects, a method includes receiving an input test signal at a test input, receiving an event signal, and passing the input test signal to a test output or blocking the input test signal from the test output based on the event signal. In certain aspects, the event signal indicates an occurrence of an event in a circuit block (e.g., a memory, a processor, or another type of circuit block). The event may include a precharge operation, opening of input latches, reset of a self-time loop, arrival of a data value at a flop in a signal path, an interrupt signal indicating an error or failure in the circuit block, or another type of event.