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    HIGH-SPEED MULTI-PORT MEMORY SUPPORTING COLLISION
    2.
    发明申请
    HIGH-SPEED MULTI-PORT MEMORY SUPPORTING COLLISION 有权

    公开(公告)号：US20220310156A1

    公开(公告)日：2022-09-29

    申请号：US17210230

    申请日：2021-03-23

    Applicant: QUALCOMM Incorporated

    Inventor： Pradeep RAJ ,  Rahul SAHU ,  Sharad Kumar GUPTA

    IPC: G11C11/418 ,  G11C11/419

    Abstract: A multi-port memory is provided that supports collision between a read port and a write port to the same multi-port bitcell. A sense amplifier reads a data bit from a multi-port bitcell when a write port to the multi-port bitcell is addressed during a system clock signal. Should a read port to the multi-port bitcell be addressed during the same system clock signal, a multiplexer selects for an output bit from the sense amplifier.

    MEMORY WITH EFFICIENT DVS CONTROLLED BY ASYNCHRONOUS INPUTS
    3.
    发明申请
    MEMORY WITH EFFICIENT DVS CONTROLLED BY ASYNCHRONOUS INPUTS 有权

    公开(公告)号：US20230139283A1

    公开(公告)日：2023-05-04

    申请号：US17517386

    申请日：2021-11-02

    Applicant: QUALCOMM Incorporated

    Inventor： Pradeep RAJ ,  Rahul SAHU ,  Sharad Kumar GUPTA ,  Chulmin JUNG

    IPC: G11C29/50 ,  G11C8/08

    Abstract: A memory is provided that is configured to practice a sleep mode without retention in which a both bitcell array and a memory periphery are powered down responsive to an assertion of sleep mode without retention control signal. The sleep mode without retention control signal is also asserted during a DVS scan to power down the bitcell array. The memory includes a power management circuit that responds to an assertion of a DVS scan control signal to prevent the assertion of the sleep mode without retention control signal from causing a power down of the memory periphery during the DVS scan. The memory periphery may thus be thoroughly tested by the DVS scan because leakage current from the bitcell array is prevented by the powering down of the bitcell array.

    AREA EFFICIENT WRITE DATA PATH CIRCUIT FOR SRAM YIELD ENHANCEMENT
    4.
    发明申请
    AREA EFFICIENT WRITE DATA PATH CIRCUIT FOR SRAM YIELD ENHANCEMENT 审中-公开

    公开(公告)号：US20190108872A1

    公开(公告)日：2019-04-11

    申请号：US15727448

    申请日：2017-10-06

    Applicant: QUALCOMM Incorporated

    Inventor： Sharad Kumar GUPTA ,  Pradeep RAJ ,  Rahul SAHU ,  Mukund NARASIMHAN

    IPC: G11C11/419

    Abstract: A memory and method of performing a write operation in a memory are disclosed. In one aspect of the disclosure, the memory includes a memory cell, a pair of bit lines coupled to the memory cell, a multiplexer, and a pull-up circuit coupled to the multiplexer. The multiplexer may be configured to select the pair of bit lines coupled to the memory cell during the write operation. To increase the write performance of the memory cell, the pull-up circuit is configured to select which of the pair of bit lines is a non-zero bit line during the write operation and to clamp the non-zero bit line through the multiplexer to approximately a power rail voltage. Thus, the pull-up circuit may increase the voltage difference between the non-zero bit line and the zero bit line during the write operation and thus decrease the area and power consumed by a boost capacitance.

    WORDLINE ADJUSTMENT SCHEME
    5.
    发明申请
    WORDLINE ADJUSTMENT SCHEME 有权

    公开(公告)号：US20170287551A1

    公开(公告)日：2017-10-05

    申请号：US15085942

    申请日：2016-03-30

    Applicant: QUALCOMM Incorporated

    Inventor： Rahul SAHU ,  Sharad Kumar GUPTA

    IPC: G11C11/419 ,  G11C11/418 ,  G11C11/412

    CPC classification number: G11C11/419 ,  G11C8/08 ,  G11C11/412 ,  G11C11/413 ,  G11C11/418 ,  G11C16/08 ,  G11C16/30

    Abstract: A memory and a method for operating a memory are provided. The memory includes a memory cell having a transistor and a wordline driver outputting a wordline coupled to the memory cell. The wordline driver adjusts a voltage level of the wordline to compensate for a parameter of the transistor. The method includes asserting a wordline voltage to access a memory cell having a transistor and adjusting the wordline voltage to compensate for a parameter of the transistor. Another memory is provided. The memory includes a memory cell and a wordline driver outputting a wordline coupled to the memory cell. The wordline driver adjusts a voltage level of the wordline based on a feedback of the wordline.

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