公开(公告)号：US20150262936A1

公开(公告)日：2015-09-17

申请号：US14645336

申请日：2015-03-11

Applicant: QUALCOMM Incorporated

Inventor： Mamta BANSAL ,  Uday DODDANNAGARI ,  Paras GUPTA ,  Ramaprasath VILANGUDIPITCHAI ,  Parissa NAJDESAMII ,  Dorav KUMAR ,  Nitin PARTANI

IPC: H01L23/538 ,  G06F17/50 ,  H01L27/02

CPC classification number: G06F17/5077 ,  G06F17/5072 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/092 ,  H01L2924/0002 ,  H04W72/0453 ,  Y02D70/00 ,  H01L2924/00

Abstract: A MOS device includes a number of standard cells configured to reduce routing congestions while providing area savings on the MOS device. The standard cells may be single height standard cells that share an n-type well isolated from other nearby n-type wells. The input and output signal pins of the single height standard cells may be configured in a lowest possible metal layer (e.g., M1), while the secondary power pins of the single height standard cells may be configured in a higher metal layer (e.g., M2). Interconnects supplying power to secondary power pins may be configured along vertical tracks and shared among different sets of standard cells, which may reduce the number of vertical tracks used in the MOS device. The number of available horizontal routing tracks in the MOS device may remain unaffected, since the horizontal tracks already used by the primary power/ground mesh are used for power connection.

Abstract translation: MOS器件包括多个标准单元，其被配置为减少路由拥塞，同时在MOS器件上提供区域节省。 标准细胞可以是共享与其他附近n型孔分离的n型井的单高度标准细胞。 单个高度标准单元的输入和输出信号引脚可以配置在最低可能的金属层（例如，M1）中，而单高度标准单元的次级电源引脚可以配置在较高的金属层（例如，M2 ）。 为次级电源引脚供电的互连可以沿着垂直轨道配置，并在不同的标准单元组之间共享，这可以减少在MOS器件中使用的垂直轨道的数量。 MOS器件中可用的水平路由轨迹的数量可能不受影响，因为主电源/接地网格已经使用的水平轨迹用于电源连接。

公开(公告)号：US20250072110A1

公开(公告)日：2025-02-27

申请号：US18454376

申请日：2023-08-23

Applicant: QUALCOMM Incorporated

Inventor： Kamesh MEDISETTI ,  Sharad Kumar GUPTA ,  Sudesh Chandra SRIVASTAVA ,  Somesh AGARWAL ,  Udayakiran Kumar YALLAMARAJU ,  Anand Ashok BALIGATTI ,  Girish T P ,  Ankur MEHROTRA ,  Gousulu KANDUKURU ,  Abhinav CHAUHAN ,  Amit KASHYAP ,  Parissa NAJDESAMII

IPC: H01L27/118

Abstract: A chip includes a merger cell including a first p-type length of diffusion (LOD) region extending in a first direction, a first n-well underneath the first p-type LOD region, a first supply rail configured to receive a first supply voltage, and a first n-tap coupling the first n-well to the first supply rail. The merger cell also includes a second p-type length of diffusion (LOD) region extending in the first direction, a second n-well underneath the second p-type LOD region, a second supply rail configured to receive a second supply voltage different from the first supply voltage, and a second n-tap coupling the second n-well to the second supply rail.

公开(公告)号：US20240038760A1

公开(公告)日：2024-02-01

申请号：US17878825

申请日：2022-08-01

Applicant: QUALCOMM Incorporated

Inventor： Manjanaika CHANDRANAIKA ,  Parissa NAJDESAMII ,  Kamesh MEDISETTI ,  Iranagouda Shivanagouda NAGANAGOUDRA

IPC: H01L27/092 ,  H01L23/528

CPC classification number: H01L27/092 ,  H01L23/5286 ,  H04B1/40

Abstract: An integrated circuit (IC), including a first row of cells including a first set of one or more complementary metal oxide semiconductor (CMOS) signal processing cells including a first diffusion region; a second row of cells including a second set of one or more CMOS signal processing cells including a second diffusion region; and a first body tie electrically coupling a first voltage rail to the first and second diffusion regions.

公开(公告)号：US20170352649A1

公开(公告)日：2017-12-07

申请号：US15174684

申请日：2016-06-06

Applicant: QUALCOMM Incorporated

Inventor： Harshat PANT ,  Mohammed Yousuff SHARIFF ,  Parissa NAJDESAMII ,  Ramaprasath VILANGUDIPITCHAI ,  Divjyot BHAN

IPC: H01L27/02 ,  H01L27/088 ,  H01L23/535

CPC classification number: H01L27/0207 ,  G06F17/5068 ,  G06F17/5072 ,  H01L21/823892 ,  H01L23/535 ,  H01L27/0886

Abstract: In an aspect of the disclosure, a MOS device for reducing routing congestion caused by using split n-well cells in a merged n-well circuit block is provided. The MOS device may include a first set of cells adjacent to each other in a first direction. The MOS device may include a second set of cells adjacent to each other in the first direction and adjacent to the first set of cells in a second direction. The second set of cells each may include a first n-well, a second n-well, and a third n-well separated from each other. The MOS device may include an interconnect extending in the first direction in the second set of cells. The interconnect may provide a voltage source to the first n-well of each of the second set of cells.