公开(公告)号：US20230290387A1

公开(公告)日：2023-09-14

申请号：US17654295

申请日：2022-03-10

Applicant: QUALCOMM Incorporated

Inventor： Pradeep RAJ ,  Rahul SAHU ,  Sharad Kumar GUPTA ,  Hemant PATEL ,  Diwakar SINGH

IPC: G11C7/10 ,  G11C7/06 ,  G11C7/12

CPC classification number: G11C7/1012 ,  G11C7/1096 ,  G11C7/106 ,  G11C7/1087 ,  G11C7/06 ,  G11C7/12

Abstract: One implementation includes a random access memory (RAM) that has a muted multiplexing functionality. For instance, a RAM may be implemented having a first outer bank, a first inner bank, a second outer bank, and a second inner bank, each coupled to a controller. Multiplexing circuits for the outer banks may be disposed adjacent the outer banks and away from the controller, whereas the multiplexing circuits for the inner banks may be disposed within or adjacent to the controller.

公开(公告)号：US20220068940A1

公开(公告)日：2022-03-03

申请号：US17004457

申请日：2020-08-27

Applicant: QUALCOMM Incorporated

Inventor： Kalyan Kumar ORUGANTI ,  Sreeram GURRAM ,  Venkata Balakrishna Reddy THUMU ,  Pradeep Jayadev KODLIPET ,  Diwakar SINGH ,  Channappa DESAI ,  Sunil SHARMA ,  Anne SRIKANTH ,  Yandong GAO

IPC: H01L27/11 ,  H01L27/088 ,  H01L29/423

Abstract: An IC includes a first memory block, a second memory block, and a first memory border cell between the first memory block and the second memory block. The first memory border cell includes a first memory core endcap to the first memory block on a first side of the cell. The first memory border cell further includes a second memory core endcap to the second memory block on a second side of the cell. The second side is opposite the first side. The first memory border cell further includes a memory gap portion between the first memory core endcap and the second memory core endcap. The memory gap portion provides a gap between the first memory core endcap and the second memory core endcap.

公开(公告)号：US20240312496A1

公开(公告)日：2024-09-19

申请号：US18669383

申请日：2024-05-20

Applicant: QUALCOMM Incorporated

Inventor： Pradeep RAJ ,  Rahul SAHU ,  Sharad Kumar GUPTA ,  Hemant PATEL ,  Diwakar SINGH

IPC: G11C7/10 ,  G11C7/06 ,  G11C7/12

CPC classification number: G11C7/1012 ,  G11C7/06 ,  G11C7/106 ,  G11C7/1087 ,  G11C7/1096 ,  G11C7/12

Abstract: One implementation includes a random access memory (RAM) that has a muted multiplexing functionality. For instance, a RAM may be implemented having a first outer bank, a first inner bank, a second outer bank, and a second inner bank, each coupled to a controller. Multiplexing circuits for the outer banks may be disposed adjacent the outer banks and away from the controller, whereas the multiplexing circuits for the inner banks may be disposed within or adjacent to the controller.