公开(公告)号：US20220310156A1

公开(公告)日：2022-09-29

申请号：US17210230

申请日：2021-03-23

Applicant: QUALCOMM Incorporated

Inventor： Pradeep RAJ ,  Rahul SAHU ,  Sharad Kumar GUPTA

IPC: G11C11/418 ,  G11C11/419

Abstract: A multi-port memory is provided that supports collision between a read port and a write port to the same multi-port bitcell. A sense amplifier reads a data bit from a multi-port bitcell when a write port to the multi-port bitcell is addressed during a system clock signal. Should a read port to the multi-port bitcell be addressed during the same system clock signal, a multiplexer selects for an output bit from the sense amplifier.

公开(公告)号：US20240221828A1

公开(公告)日：2024-07-04

申请号：US18603118

申请日：2024-03-12

Applicant: QUALCOMM Incorporated

Inventor： Pradeep RAJ ,  Rahul SAHU ,  Sharad Kumar GUPTA

IPC: G11C11/418 ,  G11C11/419

CPC classification number: G11C11/418 ,  G11C11/419

Abstract: A multi-port memory is provided that supports collision between a read port and a write port to the same multi-port bitcell. A sense amplifier reads a data bit from a multi-port bitcell when a write port to the multi-port bitcell is addressed during a system clock signal. Should a read port to the multi-port bitcell be addressed during the same system clock signal, a multiplexer selects for an output bit from the sense amplifier.

公开(公告)号：US20230290387A1

公开(公告)日：2023-09-14

申请号：US17654295

申请日：2022-03-10

Applicant: QUALCOMM Incorporated

Inventor： Pradeep RAJ ,  Rahul SAHU ,  Sharad Kumar GUPTA ,  Hemant PATEL ,  Diwakar SINGH

IPC: G11C7/10 ,  G11C7/06 ,  G11C7/12

CPC classification number: G11C7/1012 ,  G11C7/1096 ,  G11C7/106 ,  G11C7/1087 ,  G11C7/06 ,  G11C7/12

Abstract: One implementation includes a random access memory (RAM) that has a muted multiplexing functionality. For instance, a RAM may be implemented having a first outer bank, a first inner bank, a second outer bank, and a second inner bank, each coupled to a controller. Multiplexing circuits for the outer banks may be disposed adjacent the outer banks and away from the controller, whereas the multiplexing circuits for the inner banks may be disposed within or adjacent to the controller.

公开(公告)号：US20230139283A1

公开(公告)日：2023-05-04

申请号：US17517386

申请日：2021-11-02

Applicant: QUALCOMM Incorporated

Inventor： Pradeep RAJ ,  Rahul SAHU ,  Sharad Kumar GUPTA ,  Chulmin JUNG

IPC: G11C29/50 ,  G11C8/08

Abstract: A memory is provided that is configured to practice a sleep mode without retention in which a both bitcell array and a memory periphery are powered down responsive to an assertion of sleep mode without retention control signal. The sleep mode without retention control signal is also asserted during a DVS scan to power down the bitcell array. The memory includes a power management circuit that responds to an assertion of a DVS scan control signal to prevent the assertion of the sleep mode without retention control signal from causing a power down of the memory periphery during the DVS scan. The memory periphery may thus be thoroughly tested by the DVS scan because leakage current from the bitcell array is prevented by the powering down of the bitcell array.

公开(公告)号：US20190108872A1

公开(公告)日：2019-04-11

申请号：US15727448

申请日：2017-10-06

Applicant: QUALCOMM Incorporated

Inventor： Sharad Kumar GUPTA ,  Pradeep RAJ ,  Rahul SAHU ,  Mukund NARASIMHAN

IPC: G11C11/419

Abstract: A memory and method of performing a write operation in a memory are disclosed. In one aspect of the disclosure, the memory includes a memory cell, a pair of bit lines coupled to the memory cell, a multiplexer, and a pull-up circuit coupled to the multiplexer. The multiplexer may be configured to select the pair of bit lines coupled to the memory cell during the write operation. To increase the write performance of the memory cell, the pull-up circuit is configured to select which of the pair of bit lines is a non-zero bit line during the write operation and to clamp the non-zero bit line through the multiplexer to approximately a power rail voltage. Thus, the pull-up circuit may increase the voltage difference between the non-zero bit line and the zero bit line during the write operation and thus decrease the area and power consumed by a boost capacitance.

公开(公告)号：US20240312496A1

公开(公告)日：2024-09-19

申请号：US18669383

申请日：2024-05-20

Applicant: QUALCOMM Incorporated

Inventor： Pradeep RAJ ,  Rahul SAHU ,  Sharad Kumar GUPTA ,  Hemant PATEL ,  Diwakar SINGH

IPC: G11C7/10 ,  G11C7/06 ,  G11C7/12

CPC classification number: G11C7/1012 ,  G11C7/06 ,  G11C7/106 ,  G11C7/1087 ,  G11C7/1096 ,  G11C7/12

Abstract: One implementation includes a random access memory (RAM) that has a muted multiplexing functionality. For instance, a RAM may be implemented having a first outer bank, a first inner bank, a second outer bank, and a second inner bank, each coupled to a controller. Multiplexing circuits for the outer banks may be disposed adjacent the outer banks and away from the controller, whereas the multiplexing circuits for the inner banks may be disposed within or adjacent to the controller.

公开(公告)号：US20230179183A1

公开(公告)日：2023-06-08

申请号：US17922176

申请日：2021-04-29

Applicant: QUALCOMM Incorporated

Inventor： Pradeep RAJ ,  Rahul SAHU ,  Sharad Kumar GUPTA ,  Chulmin JUNG

IPC: H03K3/012 ,  H03K5/01 ,  H03K17/56

CPC classification number: H03K3/012 ,  H03K5/01 ,  H03K17/56 ,  H03K2005/00078

Abstract: Apparatuses and methods to reduce leakage current are presented. The includes a switch circuit configured to power a circuit block; a delay circuit configured to delay enabling the switch circuit powering the circuit block and to be powered down; and a bypass circuit configured to bypass the delay circuit to disable the switch circuit powering the circuit block. The method includes powering, by switch, a circuit block; powering down a delay circuit; and bypassing, by a bypass circuit, the delay circuit to disable the switch circuit powering the circuit block.