公开(公告)号：US20250132255A1

公开(公告)日：2025-04-24

申请号：US18492613

申请日：2023-10-23

Applicant: QUALCOMM Incorporated

Inventor： Channappa DESAI ,  Sunil SHARMA ,  Rahul BIRADAR ,  Ramakoti NIMMAKAYALA ,  Prasanth KONDALAMPATTI SEKAR ,  Anne SRIKANTH

IPC: H01L23/528 ,  H01L23/522

Abstract: Aspects of the present disclosure provide a filler cell that may be placed next to the active cell to reduce a current-resistor (IR) drop for the active cell. The filler cell includes an active dummy device coupled to a source of a transistor in the active cell and a rail (e.g., a ground rail or a voltage supply rail). The filler cell provides the active cell with at least one additional current path between the source of the transistor and the rail through the active dummy device, which reduces the IR drop between the source of the transistor and the rail.

公开(公告)号：US20250037753A1

公开(公告)日：2025-01-30

申请号：US18360745

申请日：2023-07-27

Applicant: QUALCOMM Incorporated

Inventor： Channappa DESAI ,  Derek YANG ,  Sunil SHARMA

IPC: G11C11/4078 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4094

Abstract: A replica column for bit line tracking of a bitcell array is disclosed that includes just one replica access transistor for each row in the bitcell array. If there are N rows, there are thus N replica access transistors in the replica column, where N is a plural positive integer. The replica column includes no other transistors besides the replica access transistors.

公开(公告)号：US20220068940A1

公开(公告)日：2022-03-03

申请号：US17004457

申请日：2020-08-27

Applicant: QUALCOMM Incorporated

Inventor： Kalyan Kumar ORUGANTI ,  Sreeram GURRAM ,  Venkata Balakrishna Reddy THUMU ,  Pradeep Jayadev KODLIPET ,  Diwakar SINGH ,  Channappa DESAI ,  Sunil SHARMA ,  Anne SRIKANTH ,  Yandong GAO

IPC: H01L27/11 ,  H01L27/088 ,  H01L29/423

Abstract: An IC includes a first memory block, a second memory block, and a first memory border cell between the first memory block and the second memory block. The first memory border cell includes a first memory core endcap to the first memory block on a first side of the cell. The first memory border cell further includes a second memory core endcap to the second memory block on a second side of the cell. The second side is opposite the first side. The first memory border cell further includes a memory gap portion between the first memory core endcap and the second memory core endcap. The memory gap portion provides a gap between the first memory core endcap and the second memory core endcap.

公开(公告)号：US20200381023A1

公开(公告)日：2020-12-03

申请号：US16430137

申请日：2019-06-03

Applicant: QUALCOMM Incorporated

Inventor： Shiba Narayan MOHANTY ,  Rahul SAHU ,  Channappa DESAI

IPC: G11C5/14

Abstract: A memory is provided with a plurality of cores that power up according to a power-up order from a first core to a final core. As the core power supply voltage for a current core powers up according to the power-up order, it triggers the power-up of a succeeding core in the power-up order responsive to the core power supply voltage exceeding the threshold voltage of a control transistor in the succeeding core.