公开(公告)号：US20240321376A1

公开(公告)日：2024-09-26

申请号：US18123852

申请日：2023-03-20

Applicant: QUALCOMM Incorporated

Inventor： Debarghya DUTTA ,  Ramakoti NIMMAKAYALA ,  Rahul SAHU

IPC: G11C29/32 ,  G11C7/06 ,  G11C29/12

CPC classification number: G11C29/32 ,  G11C7/065 ,  G11C29/1201 ,  G11C2029/3202

Abstract: A memory is provided with scan path coupled to sense amplifier output nodes. The scan path include a clocked latch that latches a data-in signal responsive to a clock signal during a scan operation to the memory. The clocked latch is not clocked during a read operation to the memory. To prevent a binary transition of the data-in signal from affecting the read operation, the scan path includes at least one blocking logic gate coupled between the clocked latch and the sense amplifier output node.

公开(公告)号：US20250132255A1

公开(公告)日：2025-04-24

申请号：US18492613

申请日：2023-10-23

Applicant: QUALCOMM Incorporated

Inventor： Channappa DESAI ,  Sunil SHARMA ,  Rahul BIRADAR ,  Ramakoti NIMMAKAYALA ,  Prasanth KONDALAMPATTI SEKAR ,  Anne SRIKANTH

IPC: H01L23/528 ,  H01L23/522

Abstract: Aspects of the present disclosure provide a filler cell that may be placed next to the active cell to reduce a current-resistor (IR) drop for the active cell. The filler cell includes an active dummy device coupled to a source of a transistor in the active cell and a rail (e.g., a ground rail or a voltage supply rail). The filler cell provides the active cell with at least one additional current path between the source of the transistor and the rail through the active dummy device, which reduces the IR drop between the source of the transistor and the rail.