公开(公告)号：US20240321376A1

公开(公告)日：2024-09-26

申请号：US18123852

申请日：2023-03-20

Applicant: QUALCOMM Incorporated

Inventor： Debarghya DUTTA ,  Ramakoti NIMMAKAYALA ,  Rahul SAHU

IPC: G11C29/32 ,  G11C7/06 ,  G11C29/12

CPC classification number: G11C29/32 ,  G11C7/065 ,  G11C29/1201 ,  G11C2029/3202

Abstract: A memory is provided with scan path coupled to sense amplifier output nodes. The scan path include a clocked latch that latches a data-in signal responsive to a clock signal during a scan operation to the memory. The clocked latch is not clocked during a read operation to the memory. To prevent a binary transition of the data-in signal from affecting the read operation, the scan path includes at least one blocking logic gate coupled between the clocked latch and the sense amplifier output node.